Physical Simulation of Drain-Induced Barrier Lowering Effect in SiC MESFETs

Abstract

The drain-induced barrier lowering (DIBL) effect in 4H-SiC MESFETs has been studied using the physical drift and diffusion model. Our simulation results showed that the high drain voltage typically applied in short-channel 4H-SiC MESFETs could substantially reduce the channel barrier and result in large threshold voltage shift. It is also found that the DIBL effect is more dependent on the ratio of the gate length to channel thickness (Lg/a), rather than the channel thickness itself. In order to minimize the DIBL effect, the ratio of Lg/a should be kept greater than 3 for practical 4H-SiC MESFETs.

Improved performance of SiC MESFETs using double-recessed structure

“…The semiinsulating substrate is modeled as a compensation-doped (vanadium) semiconductor with a high concentration (8 · 10 16 cm À3 ) of deep level impurities. The activation energy of vanadium acceptor is selected as 1.05 eV [3,7]. A two-dimensional simulator, MEDICI [8] is used in the simulation and the details of the models and simulation method are presented elsewhere [3].…”

“…To allow for high drain current, a large product of the channel doping and thickness (N · a) is required. However, a higher channel doping concentration will lower the breakdown voltage, [2] and a thick channel layer will lead to a lower aspect ratio of gate length to channel thickness (L g /a) and result in short-channel and drain-induced barrier lowering (DIBL) effects which will degrade the device and circuit performance [3]. Some researchers [4,5] suggested a buried-gate structure to suppress the trapping induced instabilities which will decrease the electrical performance of the devices operated at continuous waveband (CW).…”

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

“…The DIBL effect has been investigated analytically in Refs. [9][10][11][12][13][14][15] for the conventional MES-FET. However, it has not been studied yet for the DCFET.…”

Design, simulation and fabrication of silicon carbide metal semiconductor field effect transistors

“…In order to minimize the DIBL effect, the ratio of L g /a should be kept much greater than 3 for practical 4H-SiC MESFETs, especially when the channel doping concentration is more than 5×10 17 cm -3 . [105,106] will dominate the device performance. In order to minimize the DIBL effect, the channel layer has to be thin to maintain a large gate length to channel thickness ratio (L g /a) which in turn limits the device power capacity.…”

“…To allow for high drain current, a large product of the channel doping and thickness (N × a) is required. However, a higher channel doping concentration will lower the breakdown voltage, [77] and a thick channel layer will lead to a lower aspect ratio of gate length to channel thickness (L g /a) and result in short-channel and drain-induced barrier lowering (DIBL) effects which will degrade the device and circuit performance [105]. Some researchers suggested a buried-gate structure to suppress the trapping induced instabilities which will decrease the electrical performance of the devices operating at continuous waveband (CW).…”