Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories

Abstract

In this work, a detailed study of the physical mechanisms governing the Source Side Injection programming in ultra-scaled (down to 20nm) SiN split-gate memories is presented. Experimental measurements coupled to static and dynamic TCAD simulations are shown. In particular, we claim that adjusting the select gate voltage in moderate inversion allows for the optimization of the compromise between high electron injection and limited consumption. Then, we show that scaling the dimensions of the select gate can induce a higher consumption, while scaling the memory gate leads to lower programming energy (<1nJ) due to higher injection efficiency, suitable for low power applications.

Dynamic behavior of silicon nanocrystal memories during the hot carrier injection

“…High-k materials were integrated in 1T cell in order to improve the programming window and reliability [3,4]. Moreover split gate (1.5T) architectures were proposed to reduce the current consumption [5,6]. In a previous work on Si-nc cell we have shown the subnanojoule energy consumption during a hot carrier injection (HCI) programming operation [7].…”