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In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1 st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si 3 N 4) and hybrid Sinc/SiN based split-gate memories, with SiO 2 or Al 2 O 3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.

Microelectronic technology developments have been widely used today in MEMS or BIO (1) technologies. Plasma etching was developed more than 30 years ago and commonly used in microelectronic device processing (2). Although MEMS and BIO realizations were also based on this microelectronics standard processing method. But some process developments or sustaining were needed to achieve the high topography of such devices. We have especially developed for sub-micro and nano high topography devices application a silicon etching process based on dry plasma technology. A performed recipe allowed us to fabricate structure similar as these commonly used in MEMS and BIO devices without trenching effect and residual spacer. Silicon etched thickness of 800 shown vertical edge profile compatible with such applications.