Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories

Abstract

In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1 st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si 3 N 4) and hybrid Sinc/SiN based split-gate memories, with SiO 2 or Al 2 O 3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.

How to improve the silicon nanocrystal memory cell performances for low power applications

“…In order to reduce the operating voltages, the integration of high-k materials in the gate stack was also proposed [4,5]. Other architectures like split-gate memories [6,7] allow reducing the energy consumption of the memory, but require the addition of a select transistor, controlling the programming current.…”

Optimization of programming consumption of silicon nanocrystal memories for low power applications

“…In order to reduce the operating voltages the integration of high-k materials in the gate stack was also proposed [4,5]. Other architectures like split-gate memories [6,7] allow reducing the energy consumption of the memory, but require the addition of a select transistor, controlling the programming current. In this context, the impact of the programming parameters in 1T structures during the CHE operation (signal shape, applied voltages, programming time) was not studied in details, and the optimization of the operating scheme to reduce the energy consumption is still lacking.…”