Physics for neuromorphic computing

Marković, Danijela; Mizrahi, Alice; Querlioz, Damien; Grollier, Julie

doi:10.1038/s42254-020-0208-2

Cited by 673 publications

(410 citation statements)

References 143 publications

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“…In contrast to conventional silicon-based CMOS chips, an alternate approach to neuro-inspired hardware has been driven by the development of novel non-CMOS nanoelectronic memory devices [11]. Of these, those exhibiting resistive switching memory are especially promising for nextgeneration neuromorphic systems, offering a considerably reduced area and energy cost of emulating neurons and synapses, compared to silicon-CMOS-based approaches [12][13][14][15]. Resistive switching nanoelectronic devices were first proposed as a new class of non-volatile memory [16,17].…”

Section: Introductionmentioning

confidence: 99%

Neuromorphic nanowire networks: principles, progress and future prospects for neuro-inspired information processing

Kuncic

Nakayama

2021

Advances in Physics: X

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Nanowire networks represent a unique class of neuromorphic systems. Their self-assembly confers a complex structure to their network circuitry, embedding a higher interconnectivity of resistive switching memory (memristive) cross-point junctions than can be achieved with top-down nanofabrication methods. Coupling of the nonlinear memristive dynamics to the network topology enables intrinsic adaptiveness and gives rise to emergent non-local dynamics. In this article, we summarise the physical principles underlying the memristive junctions and network dynamics of neuromorphic nanowire networks and provide the first comprehensive review of studies to date. We conclude with a perspective on future prospects for neuromorphic information processing.

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Section: Introductionmentioning

confidence: 99%

Neuromorphic nanowire networks: principles, progress and future prospects for neuro-inspired information processing

Kuncic

Nakayama

2021

Advances in Physics: X

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“…This approach is hardware compatible as LIF neurons, leaky integrators, delays, and low pass filters are circuit elements that can be efficiently implemented in Complementary Metal Oxide Semiconductor (CMOS) technology ( Mead and Ismail, 1989 ), and bidirectional synapses could be implemented with CMOS compatible emergent nano-devices such as memristors ( Ishii et al, 2019 ; Marković et al, 2020 ; Wan et al, 2020 ). The corresponding pseudocode is given in Algorithm 1 (see supplemental information for details).…”

Section: Resultsmentioning

confidence: 99%

“…EqSpike could also be sped up by building on dedicated hardware in analog or digital CMOS ( Schemmel et al, 2010 ; Qiao et al, 2015 ; Thakur et al, 2018 ; Frenkel et al, 2019 ; Park et al., 2020 ). Emerging nanotechnologies such as memristive synapses and nanoscale spiking oscillators are compelling candidates to scale up neuromorphic hardware due to their small size, their speed, and their low energy consumption ( Marković et al, 2020 ; Milo et al, 2020 ; Sebastian et al, 2020 ; Wang et al, 2020 ; Xi et al, 2020 ). These technologies are typically prone to imperfections such as the device-to-device variability, cycle-to-cycle variability, or the non-linearity in the conductance-to-voltage response, which are known to considerably jeopardize learning in memristive neural networks ( Ishii et al, 2019 ; Zhang et al, 2020 ).…”

Section: Discussionmentioning

confidence: 99%

EqSpike: Spike-driven equilibrium propagation for neuromorphic implementations

et al. 2021

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Summary Finding spike-based learning algorithms that can be implemented within the local constraints of neuromorphic systems, while achieving high accuracy, remains a formidable challenge. Equilibrium propagation is a promising alternative to backpropagation as it only involves local computations, but hardware-oriented studies have so far focused on rate-based networks. In this work, we develop a spiking neural network algorithm called EqSpike, compatible with neuromorphic systems, which learns by equilibrium propagation. Through simulations, we obtain a test recognition accuracy of 97.6% on the MNIST handwritten digits dataset (Mixed National Institute of Standards and Technology), similar to rate-based equilibrium propagation, and comparing favorably to alternative learning techniques for spiking neural networks. We show that EqSpike implemented in silicon neuromorphic technology could reduce the energy consumption of inference and training, respectively, by three orders and two orders of magnitude compared to graphics processing units. Finally, we also show that during learning, EqSpike weight updates exhibit a form of spike-timing-dependent plasticity, highlighting a possible connection with biology.

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“…There are about 10 11 neurons and 10 15 synapses, and thus it is important to implement neurons and synapses with high density in order to mimic the brain in hardware. 7,8 Neurons are mainly composed of CMOS-based circuits, while synapses primarily comprise memristors. [9][10][11][12][13][14][15] However, circuit-based neurons are problematic for high packing density with low-cost because they are composed of a capacitor, integrator, and comparator including many transistors.…”

Section: Introductionmentioning

confidence: 99%

Co-integration of single transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

Han

Yun

et al. 2021

Preprint

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Co-integration of multi-state single transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide-semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide-semiconductor field-effect transistor (MOSFET) with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to co-integrate the neurons and synapses with additional CMOS circuits, such as a current mirror and inverter. Such co-integration can enhance packing density, reduce chip cost, and simplify fabrication procedures. Neuronal inhibition and tunability of the firing threshold voltage were demonstrated for an energy efficient and reliable neural network. The multi-state single transistor neuron with low peak power consumption of 120 nW that can control neuronal inhibition and the firing threshold voltage was achieved. Spatio-temporal neuronal functionalities are demonstrated with analyses of a fabricated neuromorphic module, which is composed of a single transistor neuron and a set of single transistor synapse. Image processing for letter pattern recognition and face image recognition is performed using a hardware-based circuit simulation and a software-based neuromorphic simulation, respectively.

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Physics for neuromorphic computing

Cited by 673 publications

References 143 publications

Neuromorphic nanowire networks: principles, progress and future prospects for neuro-inspired information processing

Neuromorphic nanowire networks: principles, progress and future prospects for neuro-inspired information processing

EqSpike: Spike-driven equilibrium propagation for neuromorphic implementations

Co-integration of single transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

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