PicoServer

Abstract

This article extends our prior work to show that a straightforward use of 3D stacking technology enables the design of compact energy-efficient servers. Our proposed architecture, called PicoServer, employs 3D technology to bond one die containing several simple, slow processing cores to multiple memory dies sufficient for a primary memory. The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency means that thermal constraints, a concern with 3D stacking, are easily satisfied. We extend our original analysis on PicoServer to include: (1) a wider set of server workloads, (2) the impact of multithreading, and (3) the on-chip DRAM architecture and system memory usage. PicoServer is intentionally simple, requiring only the simplest form of 3D technology where die are

An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

“…Taeho Kgil et al proposed new architecture for a tier 1 server called PicoServer [18]. It suggested a flattened memory hierarchy that elides intermediate caches.…”

Die-stacking Architecture

“…In addition to the caches stacking, many studies have been exploring the potential of building main memory on-chip with the help of 3D integration [31][32][33][43][44][45].…”

“…e most straightforward way is to implement a vertical bus across the layers of stacked DRAM layers to the processor cores [43][44][45]. e topology and overall architecture of the 3D stacked memory is kept the same as in the traditional off-chip memory.…”

“…Kgil et al studied the advantages of 3D stacked main memory, with respect to the energy efficiency of processors [43]. In their work, the structure of the DRAM-based main memory was not changed and was stacked directly on the processor.…”

Exploiting accelerators for efficient high dimensional similarity search

“…Much further into the future, the number of devices connected to web services in expected to reach hundreds of billions [35], and the question naturally arises as to what is the best way to satisfy this demand. Server designs based on commodity multicore processors may not be the most cost effective and energy efficient for all workloads, and there is ongoing debate over which architecture is best suited for specific workloads [2,10,19,22,27,29,31].…”