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Luk, Chi-Keung; Cohn, Robert; Muth, Robert; Patil, Harish; Klauser, Artur; Lowney, Geoff; Wallace, Steven; Reddi, Vijay Janapa; Hazelwood, Kim

doi:10.1145/1064978.1065034

Cited by 1,136 publications

(69 citation statements)

References 13 publications

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“…COMMUNICATION DRIVEN HYBRID INTERCONNECT DESIGN age) graph output (an example of a QDU graph is shown in Figure 3.3). QUAD toolset is based on PIN Dynamic Binary Instrumentation (DBI) framework [Luk et al, 2005]. QUAD traces each memory read and write access to record necessary information regarding the data communication among functions.…”

Section: Step 1: Profilingmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

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Section: Step 1: Profilingmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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“…Dynamic instrumentation tools, such as Pin [69], add instrumentation each time a selected program element is going to be executed. A just-in-time compiler is used to compile new code for the straight line code sequence starting at the instruction to be instrumented.…”

Section: Executing Test Casesmentioning

confidence: 99%

“…For each insertion, the tool transfers control to the generated sequence [69]. While dynamic techniques are advantageous in that they do not require static code modification, the time and memory overheads are generally substantially higher than that of static instrumentation [107,111].…”

Section: Executing Test Casesmentioning

confidence: 99%

Testing in Resource-Constrained Environments

Walcott-Justice¹

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In recent software development environments, resources including time, memory, and power constrain the execution of software test cases. Often the cost of running all test cases is prohibitively expensive, necessitating techniques to select test cases of the highest quality for test execution. While many test case selection and prioritization techniques exist to select test cases that are more likely to find faults, none take the resource constraints under which the tests will operate directly into consideration. Another cost in test case execution comes from structural testing. Structural testing is an important technique in which during execution test cases are also evaluated for structural coverage. This is typically performed through the use of code instrumentation. However, instrumentation incurs high overhead in terms of time and code growth, making it difficult to use in resource-constrained environments such as mobile device testing.This thesis develops and evaluates techniques for efficient and effective execution of test cases in resource-constrained environments. The first set of techniques selects high quality test cases from test suites while taking resource constraints into account. The resulting test selection is guaranteed to execute within the specified resource constraints, and the resulting test cases have the highest possible potential for overall fault detection during their constrained execution. The selected tests are additionally ordered in a way that is likely to find faults earlier in test execution rather than later. These techniques represent the first to guarantee that test selections will execute within a given constraint, and they offer a spectrum of options for selecting tests to execute in resource-constrained environments.The second set of techniques evaluates the quality of test cases during execution withi Abstract ii out the need of expensive and intrusive instrumentation. Instead, our quality evaluation techniques exploit recent hardware advances to monitor program execution. By leveraging these hardware advances, up to 90% of branch coverage and 79% of statement coverage can be determined with less time overhead compared to instrumentation. Because the techniques require little or no code modification or dynamic code insertion and can run on commodity machines, tablets, or mobile devices, the techniques also enable test case execution and evaluation on resource-constrained devices. No specialized hardware or components are required. The techniques are combined into a runtime and static testing system called THeME: Testing by Hardware Monitoring Events. THeME is a portable, extensible system, making it applicable for use in a wide range of resource-constrained environments.

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“…Using the measured contentiousness and the measured PMUs profile, including the average L2LinesIn/ms and L3LinesIn/ms, we then conduct regression analysis to determine the [ We then use a PIN [33] …”

Section: [Regression To Establish the Prediction Model] After Identifmentioning

confidence: 99%

“…To correlate the contention score to the corresponding static code regions, the number of instructions retired in each 1 ms execution interval is also sampled and recorded. After the profiling run, a PIN [33] tool is used to replay the execution. Based on the recorded instruction profile, our PIN tool identifies the hottest basic blocks that are executed during each 1 ms execution interval and assigns the corresponding contention score to these basic blocks.…”

Section: Rn-compile: Compiling For Reactive Nicenessmentioning

confidence: 99%

Mitigating Memory Resource Contention in Warehouse Scale Computers

Tang¹

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The class of modern datacenters hosting large-scale Internet services such as web-search, mail, and social networking has gained significant momentum in today's computing environments. However, these datacenters, recently coined as warehouse scale computers (WSCs), are extremely expensive to construct and operate. Improving software performance and server utilization is key to improving the efficiency and reducing the enormous cost in WSCs.Modern WSCs are constructed using commodity multicore processors, on which part of the memory subsystem is shared. When multiple applications are co-located on a multicore machine, contention for the shared memory resources, such as caches and memory bandwidth, may occur. This contention can cause severe cross-core performance interference and significantly degrade application performance. Mitigating resource contention is critical for improving application performance. However, despite the wealth of research effort on contention management, little is known about how emerging large-scale web-service applications interact with the shared memory resources on commodity processors and how this contention can be mitigated to improve the performance of these applications.In addition to performance, mitigating contention is also critical for improving the server utilization in WSCs. As multicore processors with expanding core counts continue to dominate the server market, the overall utilization of WSCs depends heavily on the consolidation of workloads to take advantage of the total computing potential provided by modern processors. However, many of the applications running in WSCs are user-facing, latency-sensitive applications with quality of service (QoS) requirements. These QoS requirements can be violated by the performance interference that can occur when multiple applications are consolidated on a single machine. As a result, the current common practice in WSCs is iii to disallow the co-location of latency-sensitive applications with other applications. This approach is undesirable as it results in low machine utilization in WSCs and millions of dollars wasted.This dissertation presents novel compilation and runtime approaches to significantly mitigate contention and thus improve performance, QoS and machine utilization in datacenters. Specifically, the main contributions of this dissertation include: 1) comprehensive investigation and characterization of the impact of memory resource sharing on industrystrength large-scale datacenter workloads, which expose new characteristics and insights contrary to recent literature; 2) the design of a heuristic based system and a runtime system to intelligently map application threads to cores to promote positive resource sharing and mitigate resource contention to improve application performance; and 3) the design of novel compilation techniques and runtime systems that statically and dynamically manipulate applications' contentious nature to enable the co-location of applications with varying QoS requirements and as a result, gr...

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Pin

Cited by 1,136 publications

References 13 publications

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Testing in Resource-Constrained Environments

Mitigating Memory Resource Contention in Warehouse Scale Computers

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