Pinned Photodiode CMOS Image Sensor TCAD Simulation: In-Depth Analysis of in-Pixel Pinning Voltage Measurement for a Diagnostic Tool

Abstract

TCAD simulations are conducted on a pinned photodiode (PPD), with the aim to reproduce the pinning voltage measurement developed by Tan et al. A thermionic model is proposed and detailed in order to explain the exponential injection occurring at an injection voltage higher than the pinning voltage, and the correct method to extract the transfer gate inversion voltage is given. Then, various non idealities are simulated, such as doping variations or doping layer shifts, the goal being to get a PPD diagnostic tool based on the pinning voltage measurement. Finally, the pinned photodiode is simulated in a real reading mode, and a charge partition mechanism is demonstrated in specific conditions.

Dark Current Sharing and Cancellation Mechanisms in CMOS Image Sensors Analyzed by TCAD Simulations

“…The 2D simulated device is composed of a PPD with its transfer gate and a floating diffusion, and of a reset transistor allowing a floating state of the floating simulated node. The photodiode is 4 µm long, and the 4T PPD device comprises the usual layers [17]: a P+ pinning and a N+ photodiode layer, an APT layer preventing leakage between the PPD and the floating node, a Vt adjust layer in the first part of the TG channel, a N+ layer used for the floating diffusion, and a Pwell isolating the floating diffusion and the reset transistor from the bulk (Fig. 3).…”

“…The root cause is supposed to be the imprecision of the doping profiles simulated in the transfer gate region, as the threshold adjust implantation and the tooling applied on APT and sensor implantations were deducted from experimental observations. Indeed, small variations on these implantation positions or concentrations have strong impacts on charge transfer and PPD FWC [17].…”

Influence of Pixel Design on Charge Transfer Performances in CMOS Image Sensors

“…When the FD area is reduced, the spill-back phenomenon appears occurring at a lower charge level for the lower FD area. Indeed, as reported in [14], when the FD is not sized correctly the phenomenon of charge partition may occur thus explaining the higher CTI values obtained at reduced FD areas.…”

“…4(a) and (c) is reduced, thus leading to a reduced efficiency of the antispill-back step. The reduction of PPD-P PPD−TG step also brings to the increase of the PPD-TG barrier [14], smoothed for V HITG > 2.7 V, which contribute to the CTI increase displayed in Fig. 8.…”

Total-Ionizing Dose Effects on Charge Transfer Efficiency and Image Lag in Pinned Photodiode CMOS Image Sensors

“…3) Charges trapping by fast interface states can occur when the charges pass through the transfer channel [11]. 4) Spillback, i.e., the charges coming back to the PPD from the FD, happens when a too large amount of charges is transferred to the FD (e.g., if it is not correctly sized [12]) which means that the FD potential is lowered down to the TG potential and then that the charges under the TG can go back to the FD once the TG switch in its OFF state. Because of all these image lag sources, the determination of the charge transfer efficiency in a 4T-pixel is an important and, at the same time, a tricky point, especially when dealing also with radiation degradation such as the dark current increase.…”