Pipelined Architecture of Multi-Band Spectral Subtraction Algorithm for Speech Enhancement

Abstract

Abstract:In this paper, a new pipelined architecture of the multi-band spectral subtraction algorithm has been proposed for real-time speech enhancement. The proposed hardware has been implemented on field programmable gate array (FPGA) device using Xilinx system generator (XSG), high-level programming tool, and Nexys-4 development board. The multi-band algorithm has been developed to reduce the additive colored noise that does not uniformly affect the entire frequency band of useful signal. All the algorithm steps have been successfully implemented on hardware. Pipelining has been employed on this hardware architecture to increase the data throughput. Speech enhancement performances obtained by the hardware architecture are compared to those obtained by MATLAB simulation using simulated and actual noises. The resource utilization, the maximum operating frequency, and power consumption are reported for a low-cost Artix-7 FPGA device.

Efficient FPGA-Based Architecture of the Overlap-Add Method for Short-Time Fourier Analysis/Synthesis

“…The SNR evaluates the noise level in the reconstructed signal. It is defined as [13] SNR dB = 10 log 10…”

“…STFT-based techniques have been implemented on Field Programmable Gate Array (FPGA) for speech enhancement [10][11][12][13], audio indexing [14], and feature extraction [15][16][17] using Xilinx System Generator (XSG). This high-level programming tool provides a library of SIMULINK blocks allowing bit and cycle accurate modeling for digital signal processing (DSP) functions.…”

Real-Time Embedded Systems: Present and Future

“…Hardware-assisted efficient embedded DSPs are essential in other application domains, too. An FPGA implementation of a multi-band real-time speech enhancement system is shown in Reference [9], which includes specific architectural optimizations for speed and energy consumption. An application-specific integrated circuit (ASIC) implementation of real-time and accuracy optimizations for arctangent calculation based on a coordinate rotation digital computer (CORDIC) is shown in Reference [10] (a trigonometric function that is essential for many embedded DSP calculations), while an automated folding scheme for efficient FPGA implementation of fast Fourier transform (FFT), an algorithm widely used in many embedded application domains, is proposed and experimentally evaluated in Reference [11].…”

A Smart Binaural Hearing Aid Architecture Based on a Mobile Computing Platform

“…The noise reduction of binaural HA has been proven to be more effective than two HA systems, which process noise independently, because the former can use more spatial information [15]. However, the binaural interconnection is the biggest challenge impeding the development of binaural HA [16][17][18][19][20]. In spite of the advances in HA technology, balancing the algorithms and user experience remains a challenge, mainly due to the limitations of current HA structures.…”