VLSI architecture design is concerned with deciding on the necessary hardware resources for carrying out computations from data and/or signal processing and with organizing their interplay such as to meet target specifications defined by marketing.The foremost concern is to get the desired functionality right. The second priority is to meet some given performance target often expressed in terms of data throughput or operation rate. A third objective, of economic nature this time, is to minimize production costs. Assuming a given fabrication process, this implies minimizing circuit size and maximizing fabrication yield such as to obtain as many functioning parts per processed wafer as possible.Another general concern in VLSI design is energy efficiency. Battery-operated equipment, such as hand-held phones, tablet and laptop computers, digital hearing aids, etc. obviously impose stringent limits on the acceptable power consumption. It is perhaps less evident that energy efficiency is also of interest when power gets supplied from the mains. One reason for this is the cost of removing the heat generated by high-performance high-density ICs.The capability to change from one mode of operation to another in very little time, the flexibility to accommodate evolving needs and/or to upgrade to future standards are other highly desirable qualities and subsumed here under the term agility. Last but not least, two distinct architectures are likely to differ in terms of the overall engineering effort required to work them out in full detail and, hence also, in their respective time to market.
AGENDADriven by dissimilar applications and priorities, hardware engineers have, over the years, devised a multitude of diverse architectural concepts that we will put into perspective in this chapter. Section 3.2, opposes program-controlled and hardwired hardware concepts before showing how their respective strengths can be combined. After the necessary groundwork for architectural analysis has been laid in section 3.3, we then discuss how to select, arrange, and improve the necessary hardware resources in an efficient way with a focus on dedicated architectures. Section 3.4 is concerned with organizing computations of combinational nature, section 3.6 extends our analysis to non-recursive sequential Table 3.4 Comparison of architectural alternatives for lossless data compression with the Lempel-Ziv-77 algorithm that heavily relies on string matching operations [21]. The dedicated hardware architecture is implemented on a reconfigurable coprocessor board built around four field-programmable gate-array components. 512 special-purpose processing elements are made to carry out string comparison subfunctions in parallel. The content-addressed symbol memory is essentially organized as a shift register thereby giving simultaneous access to all entries. Of course, the two software implementations obtained from compiling C source code cannot nearly provide a similar degree of concurrency.
Top-Down Digital VLSI Design
ExampleArchitecture General...
