Pipelined Squarer for Unsigned Integers of Up to 12 Bits

Abstract

SUMMARYThis paper proposes and analyzes a pipelining scheme for a hardware squarer that can square unsigned integers of up to 12 bits. Each stage is designed and adjusted such that stage delays are well balanced and that the critical path delay of the design does not exceed the reference value which is set up based on the analysis. The resultant design has the critical path delay of approximately 3.5 times a full-adder delay. In an implementation using an Intel Stratix V FPGA, the design operates at approximately 23% higher frequency than the comparable pipelined squarer provided in the Intel library.

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“…3.1, were obtained when sensor data were represented as 13-bit signed integers. Thus, a 13-bit signed integer multiplier and two 12-bit unsigned squarers [11] were used in the input stage. For simplicity, the modules for changing the operands to their absolute form, at the input ports of the squarers, are omitted in the figure.…”

“…The designed calculator was modelled in Verilog and implemented with Quartus Prime 18.0 with targeting an Intel Cyclone FPGA (5CSEMA5F31C6 [12]) using Intel megafunctions [13] and the squarer in [11]. Table 2 summarizes the implementation results and shows that only a small portion of the FPGA was consumed.…”