[1992] Proceedings the 19th Annual International Symposium on Computer Architecture
DOI: 10.1109/isca.1992.753352
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Pipelining and Bypassing in a VLIW Processor

Abstract: This paper describes issues involved in the bypassing mechanism for a VLIW processor and its relation to the pipeline structure of the processor. We will first describe the pipeline structure of our processor and analyze its performance and compare it to typical RISC-style pipeline structures given the context of a processor with multiple functional units. Next, we shall study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effec… Show more

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Cited by 8 publications
(13 citation statements)
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“…The average behavior of the register liveness for the interval [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] is depicted in Fig. 5, where each point represents the percentage of definitions of a given liveness averaged on all the benchmarks.…”
Section: A Results Of Register Liveness Analysismentioning
confidence: 99%
See 1 more Smart Citation
“…The average behavior of the register liveness for the interval [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] is depicted in Fig. 5, where each point represents the percentage of definitions of a given liveness averaged on all the benchmarks.…”
Section: A Results Of Register Liveness Analysismentioning
confidence: 99%
“…In [7], the authors show such design issues and present different bypassing interconnection networks that can be used for increased levels of connectivity among the functional units of the processor. The analysis includes both frequency of stalls and cycle time penalties and shows that a bypassing network that completely connects all of the function units does not provide an improvement in performance when the cycle time penalty and the area of the chip are taken into account.…”
Section: Introductionmentioning
confidence: 99%
“…Abnous and Bagherzadeh [1] studied the effects of bypassing among FUs in their VIPER VLIW processor. They concluded that a fully connected bypass network does not provide performance improvement when considering cycle time penalty and required silicon area.…”
Section: Background and Motivationmentioning
confidence: 99%
“…Ahuja et al [3] performed the initial study on the impact of partial bypass, which focused on detailing the amount of performance lost due to interlock stalls from missing bypasses on a scalar processor. Other work [1,9,12] has found that limiting the connections of the bypass network can result in little impact on performance while greatly decreasing cost.…”
Section: Related Workmentioning
confidence: 99%