Pipelining designs with loop-carried dependencies

Styles, Henry; Thomas, David B.; Luk, Wayne

doi:10.1109/fpt.2004.1393276

Cited by 11 publications

(10 citation statements)

References 6 publications

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“…The mapping of an unrolled loop onto pipelines has also been extensively studied [10]- [12]. The reconfigurable dataflow approach [12], in particular, maps loops with loopcarried dependencies onto efficient pipelines.…”

Section: B Algorithm Mapping Onto Reconfigurable Hardwarementioning

confidence: 99%

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Mapping Loop Structures Onto Parametrized Hardware Pipelines

Masle

Luk

2014

IEEE Trans. VLSI Syst.

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Abstract-This paper shows how a general form of algorithms consisting of a loop with loop dependencies carried from one iteration to the next can automatically be mapped to a parametric hardware design with pipelining and replication features. A technology-independent parametric model of the proposed design is developed to capture the variations of area and throughput with the number of pipeline stages and replications. Our model allows rapid optimization of design parameters by a few pre-synthesis operations. We present an optimization method based on the model. Our method is evaluated using three different applications implemented on a Xilinx Spartan 6 XC6SLX45T FPGA: a carry-save adder-based Montgomery multiplier, a modular exponentiation module, and an integer square root module. Our model facilitates design space exploration; it can quickly predict the area taken by our designs with less than 5% of error, and their maximum frequencies and throughputs with less than 22% of error. Our optimization method is up to 96 times faster than a full search through the design space.Index Terms-Design space exploration, field-programmable gate array (FPGA), hardware mapping, loop-carried dependencies, resource estimation.

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Section: B Algorithm Mapping Onto Reconfigurable Hardwarementioning

confidence: 99%

“…The reconfigurable dataflow approach [12], in particular, maps loops with loopcarried dependencies onto efficient pipelines. This method is more fine-grained and general than our approach, since it supports loop-carried dependencies of various sizes and loop indices determined at runtime.…”

Section: B Algorithm Mapping Onto Reconfigurable Hardwarementioning

confidence: 99%

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Masle

Luk

2014

IEEE Trans. VLSI Syst.

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“…The solution to this problem is to use a C-Slow approach, which uses multiple independent accumulation states, all cycling through the same pipelined loop [5]. For example, the textbook algorithm contains a dependency between T i and T i−1 via an addition.…”

Section: Hardware Architecture For Textbook and Updating Algorithmmentioning

confidence: 99%

Estimation of sample mean and variance for Monte-Carlo simulations

Thomas

Luk

2008

2008 International Conference on Field-Programmable Technology

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“…(v) Dynamic scheduling [8]. This approach schedules tasks at run-time making use of both online and offline parameters.…”

Section: International Journal Of Reconfigurable Computingmentioning

confidence: 99%

“…This approach does not analyze task dependency in different iterations which may result in reduced parallelism. [1,2] Control flow based GCD, counter, Filtering Multiprocessors system not addressed [3] Modulo scheduling DCT, FFT Analyze one iteration, single loop [4] Graph conversion Random graphs Less parallelism, single loop [5][6][7] Loop unrolling Random graphs, FFT, solver equalizer Single loop unrolling [8] Dynamic scheduling Fractal generation Loop unrolling not addressed, single loop [9,10] Loop fission JPEG compression, DCT, BPIC Loop unrolling not addressed, single loop…”

Section: Introductionmentioning

confidence: 99%

Multiloop Parallelisation Using Unrolling and Fission

Lam

Coutinho

et al. 2010

International Journal of Reconfigurable Computing

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A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling.

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Pipelining designs with loop-carried dependencies

Cited by 11 publications

References 6 publications

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Estimation of sample mean and variance for Monte-Carlo simulations

Multiloop Parallelisation Using Unrolling and Fission

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