Pixel Level Characterization of Pinned Photodiode and Transfer Gate Physical Parameters in CMOS Image Sensors

Abstract

A method to extract the pinned photodiode (PPD) physical parameters inside a CMOS image sensor pixel array is presented. The proposed technique is based on the Tan et al. pinning voltage characteristic. This pixel device characterization can be performed directly at the solid-state circuit output without the need of any external test structure. The presented study analyzes the different injection mechanisms involved in the different regimes of the characteristic. It is demonstrated that in addition to the pinning voltage, this fast measurement can be used to retrieve the PPD capacitance, the pixel equilibrium full well capacity, and both the transfer gate threshold voltage and its channel potential at a given gate voltage. An alternative approach is also proposed to extract an objective pinning voltage value from this measurement.

Focal-Plane Scale Space Generation with a 6T Pixel Architecture

“…Since we found no available information on models for the pinned photodiode, it is also in our interest to investigate its behavior. A technique for measuring pinned photodiode and transfer gate parameters that involves reducing the reset voltage during the integration period is presented in [10]. This type of measure may help the design of future chips and the better understanding of this chip.…”

Temperature Dependence and Dynamic Behavior of Full Well Capacity in Pinned Photodiode CMOS Image Sensors

“…4. Pinning voltage as a function of temperature: comparison between experimental data (extracted with the integral method presented in [14]) and the model of (2). The best fit has been obtained for N PPD = 2.4×10 16 cm −3 , N a = 1 × 10 18 cm −3 , and W PPD = 280 nm.…”

“…Different pinning voltage extraction techniques have been proposed in [8], [13] and [14]. In this paper, V pin has been extracted from the pinning voltage characteristic [13] with the integral method proposed by Goiffon et al in [14].…”

“…In this paper, V pin has been extracted from the pinning voltage characteristic [13] with the integral method proposed by Goiffon et al in [14]. As it can be observed in Fig.…”

“…If the PPD is reset and left in the dark with the TG accumulated, the PPD capacitance is discharged by the dark current I junc , until reaching a saturation level that corresponds to the equilibrium condition of a p-n junction. The saturation charge obtained in dark conditions and neglecting the TG leakage current is referred to as the equilibrium FWC (EFWC) [6], [14]. The open circuit voltage V OC corresponding to the EFWC can be obtained by solving…”