Pixel-parallel digital CMOS implementation of image segmentation by region growing

Morimoto, Takashi; Harada, Yoshiko; Koide, Tetsushi; Mattausch, Hans Jürgen

doi:10.1049/ip-cds:20045062

Cited by 13 publications

(3 citation statements)

References 12 publications

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“…The hardware implementation of the segmentation algorithms, is not considered much in the literature. hardware implementation for image segmentation using Seed growing method is discussed in [9]. The paper uses a cell (pixel) network as the core of the architecture to implement segmentation with some degree of parallelism.…”

Section: Overview Of the Existitng Techniquesmentioning

confidence: 99%

“…They have implemented the different blocks in the architecture as to reduce the circuit area, minimum wire length and high layout regularity. The authors combined the same segmentation architecture with feature extraction block, pattern matching block to track moving objects in [9]. They have interleaved these functions to adopt pipelining in the architecture to speed up the computation.…”

Section: Overview Of the Existitng Techniquesmentioning

confidence: 99%

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VLSI implementation of image segmentation processor for brain MRI

Shanthi¹,

Sasikumar²

2010

Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India

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In this paper we present VLSI implementation of an automatic segmentation algorithm for Magnetic Resonance Images (MRI) of brain. The FPGA architecture incorporates all the functional units to realize the algorithm. The hardware implementation for threshold based segmentation is proposed. The processor capabilities can be extended to compute volume of the brain MRI. The experimental signal analysis and the resource requirement of the target device are also presented here.

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Section: Overview Of the Existitng Techniquesmentioning

confidence: 99%

Section: Overview Of the Existitng Techniquesmentioning

confidence: 99%

VLSI implementation of image segmentation processor for brain MRI

Shanthi¹,

Sasikumar²

2010

Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India

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“…The proposed implementation architecture uses a region-growing-type image segmentation cell-network [6,7]. This cell-network realizes high-speed object segmentation from an input image.…”

Section: B Image Segmentation Cell-networkmentioning

confidence: 99%

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

Yamaoka

Morimoto

Adachi

et al. 2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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A novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching, as well as its FPGA/ASIC implementation architecture are presented. With image segmentation, we can detect all objects in the images no matter whether they are moving or not. Using image segmentation results of successive frames, we exploit pattern matching in a simple object feature space for tracking of objects. The proposed algorithm can be applied to multiple moving and still objects even in the case of a moving camera. The FPGA/ASIC implementation architecture is verified to enable realtime tracking of up to 220 objects, when realized with modern FPGA hardware [1].

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RETRACTED ARTICLE: Visualized image segmentation for multi-object tracking by weak clustering technique

Gui

Zhongyi

et al. 2018

Multimed Tools Appl

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The Editor-in-Chief has retracted this article [1], which was published as part of special issue "Multi-source Weak Data Management using Big Data", because its content has been duplicated without permission from unpublished manuscripts authored by R Kishorekumar and P Deepa, and by Priya Selvam and Santhi Balachandran. In addition, there is evidence suggesting authorship manipulation and an attempt to subvert the peer review process.

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Pixel-parallel digital CMOS implementation of image segmentation by region growing

Cited by 13 publications

References 12 publications

VLSI implementation of image segmentation processor for brain MRI

VLSI implementation of image segmentation processor for brain MRI

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

RETRACTED ARTICLE: Visualized image segmentation for multi-object tracking by weak clustering technique

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