Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

Yamaoka, Kousuke; Morimoto, Takashi; Adachi, H.; Koide, Tetsushi; Mattausch, Hans Jürgen

doi:10.1145/1118299.1118350

Cited by 16 publications

(5 citation statements)

References 3 publications

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“…This is why energy-efficient object tracking has been studied over the years [29], [30], [31], [32], [33]. Researchers have also been striving to optimize hardware for tracking tasks [34], [35], [36], [37].…”

Section: Related Workmentioning

confidence: 99%

Adaptive Subsampling for ROI-based Visual Tracking: Algorithms and FPGA Implementation

Iqbal¹,

Muro²,

Katoch³

et al. 2021

Preprint

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There is tremendous scope for improving the energy efficiency of embedded vision systems by incorporating programmable region-of-interest (ROI) readout in the image sensor design. In this work, we study how ROI programmability can be leveraged for tracking applications by anticipating where the ROI will be located in future frames and switching pixels off outside of this region. We refer to this process of ROI prediction and corresponding sensor configuration as adaptive subsampling. Our adaptive subsampling algorithms comprise an object detector and an ROI predictor (Kalman filter) which operate in conjunction to optimize the energy efficiency of the vision pipeline with the end task being object tracking. To further facilitate the implementation of our adaptive algorithms in real life, we select a candidate algorithm and map it onto an FPGA. Leveraging Xilinx Vitis AI tools, we designed and accelerated a YOLO object detector-based adaptive subsampling algorithm. In order to further improve the algorithm post-deployment, we evaluated several competing baselines on the OTB100 and LaSOT datasets. We found that coupling the ECO tracker with the Kalman filter has a competitive AUC score of 0.4568 and 0.3471 on the OTB100 and LaSOT datasets respectively. Further, the power efficiency of this algorithm is on par with, and in a couple of instances superior to, the other baselines. The ECO-based algorithm incurs a power consumption of approximately 4 W averaged across both datasets while the YOLO-based approach requires power consumption of approximately 6 W (as per our power consumption model). In terms of accuracy-latency tradeoff, the ECO-based algorithm provides near-real-time performance (19.23 FPS) while managing to attain competitive tracking precision.

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Section: Related Workmentioning

confidence: 99%

Adaptive Subsampling for ROI-based Visual Tracking: Algorithms and FPGA Implementation

Iqbal¹,

Muro²,

Katoch³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Recently, image segmentation have been applied in a number of areas such as Medical Imaging for the detection of brain tumor or the study of brain development of neonatal brain from Magnetic Resonance Imaging (MRI) scanning [1,2,3,4], improvement of irregularity detection in biometric fingerprint [5], landscape analysis of remotely sensed satellite images [6], also for object detection in still and moving images [7] .…”

Section: Introductionmentioning

confidence: 99%

Image Segmentation using Multi-Threshold technique by Histogram Sampling

Gurung¹,

Tamang²

2019

Preprint

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The segmentation of digital images is one of the essential steps in image processing or a computer vision system. It helps in separating the pixels into different regions according to their intensity level. A large number of segmentation techniques have been proposed, and a few of them use complex computational operations. Among all, the most straightforward procedure that can be easily implemented is thresholding. In this paper, we present a unique heuristic approach for image segmentation that automatically determines multilevel thresholds by sampling the histogram of a digital image. Our approach emphasis on selecting a valley as optimal threshold values. We demonstrated that our approach outperforms the popular Otsu's method in terms of CPU computational time. We demonstrated that our approach outperforms the popular Otsu's method in terms of CPU computational time. We observed a maximum speed-up of 35.58× and a minimum speed-up of 10.21× on popular image processing benchmarks. To demonstrate the correctness of our approach in determining threshold values, we compute PSNR, SSIM, and FSIM values to compare with the values obtained by Otsu's method. This evaluation shows that our approach is comparable and better in many cases as compared to well known Otsu's method.

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“…Hardware accelerators assist central processing units (CPUs) in speeding up computations of complex algorithms in various fields, such as video/image processing (Yamaoka et al, 2006;Jan et al, 2015;Taibo et al, 2011), signal processing (Lee et al, 2013) and various mathematical calculations (Tian and Benkrid, 2010;Okuyama et al, 2012;Rostrup et al, 2013). Graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) are two types of dominantly used hardware accelerators (Chung et al, 2010).…”

Section: Introductionmentioning

confidence: 99%

pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing

Wang

Bolić

Parri

2017

IJHPCN

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This paper presents an ameliorated design of pvFPGA, which is a novel system design solution for virtualising an FPGA-based hardware accelerator by a virtual machine monitor (VMM). The accelerator design on the FPGA can be used for accelerating various applications, regardless of the application computation latencies. In the implementation, we adopt the Xen VMM to build a paravirtualised environment, and a Xilinx Virtex-6 as an FPGA accelerator. The data transferred between the x86 server and the FPGA accelerator through direct memory access (DMA), and a streaming pipeline technique is adopted to improve the efficiency of data transfer. Several solutions to solve streaming pipeline hazards are discussed in this paper. In addition, we propose a technique, hyper-requesting, which enables portions of two requests bidding to different accelerator applications to be processed on the FPGA accelerator simultaneously through DMA context switches, to achieve request level parallelism. The experimental results show that hyper-requesting reduces request turnaround time by up to 80%.Keywords: field-programmable gate array; FPGA; hardware accelerator; virtualisation; hyperrequesting; streaming pipeline; DMA context switch.Reference to this paper should be made as follows: Wang, W., Bolic, M. and Parri, J. (2017) 'pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing', Int.

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Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking

Cited by 16 publications

References 3 publications

Adaptive Subsampling for ROI-based Visual Tracking: Algorithms and FPGA Implementation

Adaptive Subsampling for ROI-based Visual Tracking: Algorithms and FPGA Implementation

Image Segmentation using Multi-Threshold technique by Histogram Sampling

pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing

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