Placement and Routing by Overlapping and Merging QCA Gates

Fontes, Geraldo; Silva, Pedro Arthur R. L.; Nacif, José Augusto M.; Neto, Omar P. Vilela; Ferreira, Ricardo

doi:10.1109/iscas.2018.8351001

Cited by 39 publications

(9 citation statements)

References 14 publications

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“…Future work could also include data-flow merging, which identifies graph similarities to generate a dedicated and straightforward reconfigurable architecture by minimizing the routing resources [Moreano et al 2005]. We also plan to compare SA-based placement to genetic [Silva et al 2006] and divide-and-conquer search [Fontes et al 2018] approaches.…”

Section: Discussionmentioning

confidence: 99%

Design Exploration of Machine Learning Data-Flows onto Heterogeneous Reconﬁgurable Hardware

Oliveira¹,

Canesche²,

Reis³

et al. 2020

Anais Do XXI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2020)

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Machine/Deep learning applications are currently the center of the attention of both industry and academia, turning these applications acceleration a very relevant research topic. Acceleration comes in different ﬂavors, including parallelizing routines on a GPU, FPGA, or CGRA. In this work, we explore the placement and routing of Machine Learning applications dataﬂow graphs onto three heterogeneous CGRA architectures. We compare our results with the homogeneous case and with one of the state-of-the-art tools for placement and routing (P&R). Our algorithm executed, on average, 52% faster than Versatile Place&Routing (VPR) 8.1. Furthermore, a heterogeneous architecture reduces the cost without losing performance in 76% of the cases.

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Section: Discussionmentioning

confidence: 99%

Design Exploration of Machine Learning Data-Flows onto Heterogeneous Reconﬁgurable Hardware

Oliveira¹,

Canesche²,

Reis³

et al. 2020

Anais Do XXI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2020)

Self Cite

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“…The scalability is improved but still unsatisfactory due to the sparse nature of the process in the placement phase. Scalability is feasible with the application of a divide-and-conquer strategy [27] to avoid the rapid growth in complexity. In this methodology, for each graph level, the initial weight of 1 is assigned for the distance in clocking zones of each internal partition.…”

Section: Tile Based Approachesmentioning

confidence: 99%

“…Next, the merge process overlaps both solutions to generate the final layout, as shown in Figure 17b. However, the largest evaluated circuit in [27] has 102 gates. A more efficient partition strategy is required to handle larger circuits inside a tiled clocking scheme.…”

Section: Tile Based Approachesmentioning

confidence: 99%

“…In this paper, we review the current state-of-the-art of FCN P&R. We discuss meta-heuristics algorithms [21], graph node duplication [22], graph partitioning [23], trade-offs between wire crossing minimization and area overhead [24], orthogonalization P&R techniques [25], clocking constraint bypassing [26], and divide-and-conquer [27] approaches.…”

Section: Introductionmentioning

confidence: 99%

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Survey on Placement and Routing for Field-Coupled Nanocomputing

Formigoni

Ferreira

Nacif

2021

JICS

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CMOS technology is reaching power, thermal, and physical limits at an alarming pace. As a response, post-silicon research investigates alternative technologies to perform computation. Field-Coupled Nanocomputing (FCN) presents low power dissipation, high frequencies, and room temperature operation. Nevertheless, FCN imposes several challenges in the development of efficient and scalable CAD tools. The placement and routing step is especially tricky in FCN compared to CMOS because of synchronization issues inherent to these technologies, such as path balancing and reconvergent paths. In this work, we survey the state-of-art of placement and routing algorithms for FCN. We describe the most recent FCN placement and routing algorithms, highlighting their limitations and, finally, presenting future work directions.

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“…Currently, software-based development tools are scarce and may require minutes to hours to find a good mapping [9]. Several heuristics to solve these problems have been presented based on simulated annealing [10]- [12], SAT-solver [13], greedy approach [14], [15], genetic algorithm [16], integer linear programming [9], split-andmerge [17], and deep learning [18], [19].…”

Section: Introductionmentioning

confidence: 99%

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays

Vieira

Canesche

Bragança

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Coarse-grained reconfigurable architectures (CGRA) are a power-efficient approach for hardware accelerators. However, there are few EDA tools for CGRA. We develop hardware-based placement and routing (P&R) for fully-pipelined CGRA mapped as an FPGA overlay. The key idea is to use the available FPGA resources to replicate several mapping units, thus exploring parallel execution, area/execution time trade-offs, and achieving near-optimal mapping solutions. Furthermore, our P&R provides portability and an incremental run-time approach. In comparison to VPR and CGRA-ME tools and a time-multiplexer approach, our spatial mapping reduces the P&R execution time, and it improves the performance up to hundreds of Gops/s by using fully-pipelined architectures.

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Placement and Routing by Overlapping and Merging QCA Gates

Cited by 39 publications

References 14 publications

Design Exploration of Machine Learning Data-Flows onto Heterogeneous Reconﬁgurable Hardware

Design Exploration of Machine Learning Data-Flows onto Heterogeneous Reconﬁgurable Hardware

Survey on Placement and Routing for Field-Coupled Nanocomputing

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays

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