Placement-aware partial reconfiguration for a class of FIR-like structures

Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters

“…Level log n (Llog(n)) X(n) similar to the solution proposed in [1] and [6]. Due to lack of space we avoid detailed explanation of the solution to JFD problem for a given tour.…”

“…In [1] and [6] we studied the JFD problem for a given sequence of filter designs. The solution to JFD for a given tour is very …”

“…However we rely on other approaches to consider physical design of filters that are generated using the joint optimization technique. In [6] we proposed a heuristic to find a mapping between partially reconfigurable modules (PRMs) and the physical regions on FPGA to reduce the reconfiguration overhead under area constraints. Furthermore in [11] we studied floorplanning and sequencing problem to reduce the reconfiguration time overhead.…”

“…Furthermore in [11] we studied floorplanning and sequencing problem to reduce the reconfiguration time overhead. We believe that physical design stage ( [6] and [11]) and structure design stage can be decoupled from each other. Thus in this work we determine the reconfiguration overhead based on the size of the modules that need to be reconfigured instead of counting the number of frames.…”

“…Recent support for dynamic partial reconfiguration (DPR) in Xilinx FPGAs also enables the modification of a system's architecture by loading or swapping logic blocks in user-defined reconfigurable regions while the FPGA device is operational. Although this provides support for multi-mode operations at the hardware level, the reconfiguration overheads commonly associated with DPR and their sensitivity to placement and routing of reconfigurable regions can have adverse effects on system performance [1] [6]. This is particularly problematic in multi-mode systems that cycle through different modes with high frequency since the impact of reconfiguration overhead can be quite significant.…”