Plasma Etching Methods for the Formation of Planarized Tungsten Plugs Used in Multilevel VLSI Metallizations

Abstract

The vias between two levels of metal interconnect in a multilevel metal system are filled using either selective or nonselective chemical vapor deposited (CVD) tungsten. Excess tungsten is then removed from the surface of the interlayer dielectric using planarization and etch back which leaves the vias filled with tungsten plugs. The uniformity of the etch‐back process can be effected by “micro‐loading” which causes local accelerated etching of the tungsten in the vias. Other nonuniformities in etch rate, resulting in trenching around the periphery of the tungsten vias, can be caused by contaminants in the CVD reactor chamber which are incorporated in the deposited film. Methods for eliminating such problems and optimizing coverage of the plugs by the overlying metal are described.

Concept and processing of buried photomasks

“…Whole topography is then capped by a directionally deposited W layer. After "lift-off" of the resist : b) c) and d) trenches of Si02 filled with 150 nm of W. process consists of photoresist coating (1.8 03BCm thick HPR 204), flood exposing (300 mJ/cm2), 250 ° C post exposure baking and plasma etching under conditions which etch W and resist at the same rate [11]. No roughness has been measured over the clear areas on the mask, even when the etching process includes an overetch time of several minutes.…”

Integrated Chemical Vapor Deposition and Plasma Etchback of Tungsten in a Multichamber, Single‐Wafer System

“…Integrated circuits which utilize contacts and vias with vertical wall profiles formed within the interlevel SiO2 layer offer significant step coverage challenges for metal deposition which may be overcome by low-pressure chemical vapor deposition (LPCVD) techniques. Tungsten has been studied more extensively than any other material for these applications and continues to gain acceptance for contact and via filling or "plug" technologies (1)(2)(3).…”

“…tive regions to form new devices that were not previously present in the system. The first real commercial application of deletive redundancy procedures involved a certain design for 64K dynamic random access memories (DRAMs) (3). For this purpose a focused laser pulse from a Q-switched Nd:YAG laser was used to melt the conductor line and cause an opening ( 4).…”

Mechanism for the Local Planarization of Microscopically Rough Surfaces by Drying Thin Films of Spin‐Coated Polymer/Solvent Solutions

“…The yield and reliability of the devices produced often depend on the degree of smoothness of the polymer film. Finally, polymer films are becoming increasingly important as sac-rificial layers for etch-back processes (14)(15)(16)(17)(18)(19)(20)(21) in which polymer is spin coated on some topographically rough substrate that may be an insulator such as phosphosilicate glass or a conductor such as tungsten. The effect of the polymer coating is again to smooth the substrate.…”