Plasma immersion ion implantation as an alternative doping technology for ULSI

Semiconductor applications of plasma immersion ion implantation

“…Shallow junctions can be accomplished using low energy in conventional beam-line ion implantation and rapid thermal annealing making use of the low thermal budget. Unfortunately, a conventional beam-line ion implantation encounters problems such as small throughput and poor beam performance as a low-energy tool [35,36]. Moreover, three-dimensional structures with large aspect ratios are difficult to dope using conventional ion implantation, and PIII, also called PD, has attracted much attention.…”

“…Figure 1 depicts typical applications of PIII to ULSI silicon processing [35]. Examples shown here include trench sidewall doping of deep trench-based and stack capacitor-based dynamic random access memory (DRAM), gate oxide processing, and polysilicon gate doping.…”

“…In addition, as the node dielectric thickness diminishes, the n-type dopant concentration on the electrodes must be increased to mitigate the depletion capacitance. PIII as a conformal trench sidewall doping technique is thus very attractive and the process has recently been demonstrated in a deep trench with an aspect ratio of 35 : 1 [35]. Figure 2 shows a SEM micrograph of an array in a DRAM cell consisting of 6 µm deep and 0.175 µm wide trenches.…”