Plasma Ion Bombardment Induced Heat Flux on the Wafer Surface in Inductively Coupled Plasma Reactive Ion Etch

Abstract

Plasma plays an important role in semiconductor processes. With the recent miniaturization and integration, the control of plasma became essential for success in the critical dimension of a few nanometers and etch narrow and deep holes with their high aspect ratios. Recently, the etching process has reached physical limitations due to a significant increase in wafer surface temperature under the elevated amount of RF power, affecting not only the warpage phenomenon, but also etching uniformity and etching profiles. Therefore, the plasma characteristics are identified using an invasive single Langmuir probe (SLP) for wafer temperature diagnosis. Optical data is obtained through a non-invasive optical emission spectroscopy (OES) and the plasma parameters are derived to compare and verify with the SLP. Two variables, electron temperature and electron density, are substituted for the heat flux formula to derive the heat flux according to the location. Using a wafer-type temperature sensor, the trends of the derived heat flux values towards wafer chuck were investigated. This study presents a method to calculate heat flux values in real time, anticipate wafer temperatures, and potentially illuminate existing ion heating problems.

On reactive Ion Etching of Parylene-C with Simple Photoresist Mask for Fabrication of High Porosity Membranes to Capture Circulating and Exfoliated Tumor Cells

“…It has been reported that having high porosity with narrow pore-to-pore spacing (i.e., S smaller than half of the cell diameter) is critical in improving the sample processing The transition of the photoresist shape is consistent with the surface tension caused shape change after photoresist melting [29,30]. It is also well known that the ion bombardment of the RIE process can heat the sample surface [31,32]. Therefore, we hypothesize that ion bombardment from the Vertical Sidewall RIE recipe have high enough energy to melt the photoresist mask that causes vertical sidewalls in parylene pores.…”

Enhanced temperature uniformity of electrostatic chuck: ceramic surface contact ratio and backside gas pressure

“…Conventional holding and cooling the wafer-temperature from the wafer backside on ESC should also include the additional heating amount appears on the front side of the wafer from the increased ion bombardment of the plasma. [8][9][10] Wafer-temperature control by heat source has received considerable attention, and several coolant modeling has been patented. 11,12) Nevertheless, only a few scientific papers have been published on the design of backside gas flows that interact most closely with a wafer.…”