Plating Technology for the Silicon and Glass Interposers

春木, 陽介; 縫田, 知宏

doi:10.4139/sfj.66.43

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…In order to uniformly distribute current between the stipeshaped positive and negative electrodes in the deep-UV LED devices, the TSVs of the Si-PKG were made in elongated trench-like shape with a width of 40 μm according to the LED electrode patterns ( Figure 2). The conventional process of electroplating for round-shaped vias was improved 15 . An x-ray CT image after electroplating is shown in Figure 3.…”

Section: Si-pkg Structurementioning

confidence: 99%

Development of silicon wafer packaging technology for deep UV LED

Chiba

Suzuki

Yasuda

et al. 2020

Electrical Engineering Japan

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This paper reports a deep‐ultraviolet LED (deep‐UV‐LED) package based on silicon MEMS process technology (Si‐PKG). The package consists of a cavity formed by silicon crystalline anisotropic etching, through‐silicon vias (TSVs) filled with electroplated Cu, bonding metals made of electroplated Ni/AuSn and a quartz lid for hermetic sealing. A deep‐UV LED die is directly mounted in the Si‐PKG by AuSn eutectic bonding without a submount. It has advantages in terms of size, heat dissipation, light utilization efficiency, productivity and cost over conventional AlN ceramic packages. We confirmed a light output of 30 mW and effective reflection on Si (111) cavity slopes in the Si‐PKG. Based on simulation, further improvement of the optical output is expected by optimizing DUV‐LED die mount condition.

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Section: Si-pkg Structurementioning

confidence: 99%

Development of silicon wafer packaging technology for deep UV LED

Chiba

Suzuki

Yasuda

et al. 2020

Electrical Engineering Japan

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Ultracompact Silicon Wafer Packaging of Deep UV LED with Excellent Cooling Performance and Light Utilization Efficiency

Chiba

Suzuki

Yasuda

et al. 2020

2020 IEEE 33rd International Conference on Micro Electro Mechanical Systems (MEMS)

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Recent Progress of TGV Technology for High Performance Semiconductor Packaging

Seok,

Jung

2024

J Weld Join

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In recent semiconductor packaging, the adoption of through silicon via (TSV) technology has become crucial for the integration of 2.5 and 3D Si chips, and interposers. The TSV offers significant advantages including high interconnect density, shortened signal pathways, and improved electrical performance. However, challenges such as electrical loss, substrate warpage, and high manufacturing costs are associated with TSV implementation. In contrast, glass-based through-glass vias (TGVs) exhibit promising characteristics such as excellent insulation properties, cost-effectiveness, and variable coefficient of thermal expansion (CTE) values that mitigate warpage in stacked devices. Moreover, they facilitate miniaturization and support high-frequency applications. This paper provides an overview of recent advancements in glass substrate, TGV drilling techniques, functional layer depositions, and Cu-filling processes in semiconductor packaging evolution.

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Plating Technology for the Silicon and Glass Interposers

Cited by 4 publications

References 6 publications

Development of silicon wafer packaging technology for deep UV LED

Development of silicon wafer packaging technology for deep UV LED

Ultracompact Silicon Wafer Packaging of Deep UV LED with Excellent Cooling Performance and Light Utilization Efficiency

Recent Progress of TGV Technology for High Performance Semiconductor Packaging

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