PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

Abstract

PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms.Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLX's wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through interinstruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.

Fast parallel table lookups to accelerate symmetric-key cryptography

“…We use the PLX toolset [12][17] to generate execution profiles for each cipher. For baseline performance data, we implement the ciphers in assembly using a RISC-like instruction set, which is shown in Table 2.…”

“…superscalar) and newer technology like wordsize scaling [11] [12]. We then compare these results to the speedups obtained when ptlu is added to the base instruction set.…”

“…Wordsize scaling, which was first introduced in the PLX multimedia ISA [11] [12], allows an instruction set to be synthesized into processors with different wordsizes. By increasing the wordsize, more subwords can be packed in a word and processed in parallel without increasing the number of instructions executed.…”

“…We then describe how to accelerate and parallelize these table lookups by using a new ptlu instruction (Section 3). In Section 4, we compare the performance benefits of our proposal with those of other architectural techniques such as superscalar execution and wordsize scaling [11] [12]. Section 5 reviews the related past work, and Section 6 is the conclusion.…”

Refining instruction set architecture for high-performance multimedia processing in constrained environments

“…Existing ISAs fall short of meeting all three criteria simultaneously. Based on our study of first and second-generation multimedia ISAs [2,12,23], we have selected the most useful multimedia instructions whose implementations are expected to be low in cost and power. To this set, we added new architectural features for even higher performance.…”