pMOS transistor with embedded SiGe: Elastic and plastic relaxation issues

Elastic Relaxation Evaluation in SiGe/Si Hetero-Epitaxial Structures

“…Lower compressive stress in the SiGe alloy is observed for the smallest windows of 3x3 μm 2 , while no significant impact of the size is observed for bigger windows. Data are in line with [15] and in good agreement with recent results obtained by the nano-beam diffraction technique, which showed that for SiGe channel pFETs, strain relaxation was observed only for the narrowest devices studied [16], which correspond to 100 nm width while for devices with 1 and 10 μm width the strain relaxation (or uniaxial stress) was only observed at the borders of the STI. The dependence on the biaxial strain (ε ) and the Ge content (x) of the Si-Si, Si-Ge, and Ge-Ge phonon frequencies of the Raman spectrum of the SiGe layer, (…”

“…For all the studied samples strain relaxation was observed for window sizes smaller than 5 μm 2 [15] (see Fig. 10.a), while no Ge content variations with the window sizes were obtained for window sizes larger than 1 μm 2 (see Fig.…”

“…This result points out the importance of elastic relaxation at small window sizes, where the recess and pre-epi bake conditions prior to epitaxial deposition can influence the shape of the layers. The nonuniformity of the contour of the layers at the edges by local thickening of the window edges and/or convex corners may significantly affect the elastic relaxation for small windows [15]. …”

Stress Characterization of Selective Epitaxial Si1-xGex Deposition for Embedded Source/Drain Before and After Millisecond Laser Anneal

“…Moreover, slightly lower average stress levels across the measurement sites are obtained for the patterned case. This can be partly understood by a decrease of the effective compressive stress levels at the edges of the SiGe alloy for small window sizes (7,9), owing to the presence of elastic relaxation processes. SiGe:B epitaxial layer on Si after a 12 keV C implantation at a dose of 1·10 15 cm -2 on the left side of the studied wafers.…”

Strain Engineering of Nanoscale Si P-Type Metal-Oxide-Semiconductor Field-Effect Transistor Devices with SiGe Alloy Integrated with Contact-Etch-Stop Layer Stressors

“…10 Moreover, a thickening of SiGe layer next to the spacer in the case of strained P MOSFETs is demonstrated to have a 40% drive current improvement in comparison to Si reference devices. [11][12] Recently, the mobility gain of at least +50% is successfully reached in a 60 nm gate length (L g ) with a long SiGe channel. 13 The researchers also reported that a higher hole mobility material like epitaxial growth of Ge layer is required when P MOSFETs is beyond 15 nm node technology of.…”