PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test

Abstract

In sub-70nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. We propose a Power-Managed Scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. We also discuss some practical implementation challenges that arise when the proposed scheme is employed on industrial designs. Experimental results on benchmark circuits and industrial designs show a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.

Investigation into voltage and process variation-aware manufacturing test

“…• Performing the test at a supply voltage and clock frequency setting that minimises power consumption [91] In this thesis, the problem of power constrained testing (which is primarily concerned with reducing switching activity during test) is considered orthogonal to the problem of testing in the presence of variation, i.e. the problems can be solved independently and the solutions can be applied together.…”

“…Further research should be conducted to find tests for DVFS designs that achieve high test quality at a low total test cost. On a related topic, studies have been performed on the cost of very-low-voltage testing [114] and on selecting a supply voltage and clock frequency setting for saving power during test [91], but no study has addressed the trade-off between test application time and test quality for DVFS designs. Scaling the clock frequency may also influence how delay fault testing should be performed.…”

Test strategies for low power devices

“…During test, gate leakage power can be reduced by DFT or ATPG techniques [14]. For example, the inputs of a gate can be carefully set so that the number of the on-transistors in the gate is reduced, without changing its output value.…”

“…But this may be difficult since dynamic power dissipation during scan shift is directly proportional to the scan shift frequency. To overcome this difficulty, a new scan architecture is proposed in [14] which uses the on-chip power management infra-structure to reduce the voltage during scan shift. The authors show that both leakage power and dynamic power are considerably reduced through voltage scaling, permitting faster shift.…”

“…The PMScan architecture of [14] is also applicable for IDDQ and burnin tests, although PMScan has not been applied for reliability tests so far.…”