1999
DOI: 10.1117/12.346224
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PN and SOI wafer flow process for stencil mask fabrication

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Cited by 14 publications
(8 citation statements)
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“…The main success of this first fabrication was the fact, that existing chip manufacturing process steps of the high-volume facility could be used and no special process development was necessary, except the very last step of Si membrane etching which was done with a process as described in earlier papers on our 6" stencil mask development [7]. The structures on the first 8" stencil mask have structure sizes in the order of 200nm.…”
Section: Asml Alignment Systemmentioning
confidence: 99%
“…The main success of this first fabrication was the fact, that existing chip manufacturing process steps of the high-volume facility could be used and no special process development was necessary, except the very last step of Si membrane etching which was done with a process as described in earlier papers on our 6" stencil mask development [7]. The structures on the first 8" stencil mask have structure sizes in the order of 200nm.…”
Section: Asml Alignment Systemmentioning
confidence: 99%
“…16. The wafer consists of a 340-nm thin silicon layer on top of 400 nm of silicon oxide, 500 μm of bulk silicon, and a silicon nitride etch mask on the backside.…”
Section: A Sample Fabricationmentioning
confidence: 99%
“…Our fabrication process is similar to the one described in Ref. 9. After having produced the membranes with a size of 0.6ϫ 0.6 mm 2 , we cover the wafers with the membranes with a 100 nm thin layer of polyimide ͑T-10001 from Brewer Science Inc.͒ using an adhesion promoter APX-K1 from the same company.…”
Section: Sample Fabrication Proceduresmentioning
confidence: 99%