2014
DOI: 10.1109/tcsi.2013.2284172
|View full text |Cite
|
Sign up to set email alerts
|

Polar Quantizer for Wireless Receivers: Theory, Analysis, and CMOS Implementation

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
12
0

Year Published

2016
2016
2022
2022

Publication Types

Select...
7
2

Relationship

0
9

Authors

Journals

citations
Cited by 21 publications
(12 citation statements)
references
References 29 publications
0
12
0
Order By: Relevance
“…Specifically, we consider a wideband downlink multi-user massive MIMO-OFDM system and focus on the case of utilizing a few amplitude bits and a moderate number of phase bits in the polar transmitter. In modern CMOS technologies, the maximum achievable amplitude resolution is decreased with continuous scaling of low supply voltage and device feature size, whereas the phase resolution is increased by the faster transition times and higher maximum oscillation frequency of nanoscale CMOS [10], [11]. Therefore, we argue that a higher number of phase bits is a feasible assumption.…”
Section: Introductionmentioning
confidence: 89%
See 1 more Smart Citation
“…Specifically, we consider a wideband downlink multi-user massive MIMO-OFDM system and focus on the case of utilizing a few amplitude bits and a moderate number of phase bits in the polar transmitter. In modern CMOS technologies, the maximum achievable amplitude resolution is decreased with continuous scaling of low supply voltage and device feature size, whereas the phase resolution is increased by the faster transition times and higher maximum oscillation frequency of nanoscale CMOS [10], [11]. Therefore, we argue that a higher number of phase bits is a feasible assumption.…”
Section: Introductionmentioning
confidence: 89%
“…In addition, the polar architecture has a power efficiency gain of up to 3 dB compared to the Cartesian, due to the omission of I/Q signal summation [9]. Moreover, a comprehensive analytical study followed by a CMOS implementation of a polar quantizer chip prototype demonstrated the superiority of signal-to-quantization-noise ratio improvement compared to rectangular (I/Q) quantizer [10]. It also showed that the maximum quantization error of large-amplitude input signals is dominated by the phase resolution.…”
Section: Introductionmentioning
confidence: 99%
“…Analytical and measurement results of wireless receivers equipped with polar quantizers have been provided in [23] showing that polar quantization offers a significant boost in signal-to-quantization noise ratio (SQNR) as compared to I/Q quantization under Gaussian signaling. Effectively, this means that polar quantizers would need fewer number of bits (NoBs) to recover the signal as compared to I/Q quantizers.…”
Section: Arxiv:220505850v1 [Csit] 12 May 2022mentioning
confidence: 99%
“…Second, phase quantizers can be implemented using one-bit ADCs that consist of simple comparators, and they consume negligible power (in the order of milliwatts). As given in [41], the implementation based on time-to-digital converters (TDCs) can also be adopted to further reduce the area and power consumption of the phase quantizer. On the other hand, phase modulation has an important and practical layering feature enabling the quantizer and detector design separation in low-resolution ADC based communications.…”
Section: B Receiver Architecturementioning
confidence: 99%