PORA: A Physarum-inspired obstacle-avoiding routing algorithm for integrated circuit design

Guo, Wenzhong; Huang, Xing

doi:10.1016/j.apm.2019.10.027

Cited by 25 publications

(9 citation statements)

References 32 publications

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“…In the octilinear case, the improvements on the total wire length are −9.9% ∼ + 47.1% and −17.4% ∼ + 11.5% compared with [55] and Huang et al [36], −12.48% ∼ + 14.62 in Chow, −15.4% ∼ + 10.26% in PSO, −17.6% ∼ + 11.57% in FH-OAOS, and −9.2% ∼ + 15.77% in PORA. Compared with the latest research in 2020 [48], the proposed approach achieves better performance in most cases of both rectilinear and octilinear routing. [36], CHOW [56], PSO [49], FH-OAOS [50], PORA [48] and ours on wire length.…”

Section: B Experimental Results and Observationsmentioning

confidence: 88%

“…Compared with the latest research in 2020 [48], the proposed approach achieves better performance in most cases of both rectilinear and octilinear routing. [36], CHOW [56], PSO [49], FH-OAOS [50], PORA [48] and ours on wire length.…”

Section: B Experimental Results and Observationsmentioning

confidence: 88%

“…We compared our algorithms with those presented in [24], [36], [55] in the 2D rectilinear and octilinear planes, PORA [48], PSO [49], FH-OAOS [50], and Chow et al [56], all works were proposed from 2006 to 2020. There are totally 12 test cases used in [24] and Table 4 lists the total wire lengths of these algorithms.…”

Section: B Experimental Results and Observationsmentioning

confidence: 99%

“…A sharing factor and a pathlength factor were introduced to trade-off wire length for delay. Researches presented a heuristic maze routing-based approach for constructing large scale OARSMTs [43]- [48]. These methods of maze routing mentioned so far only take the rectilinear cases into account.…”

Section: Steiner Problem and Current Related Work A The Steinermentioning

confidence: 99%

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An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

2020

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The rectilinear/octilinear Steiner problem is the problem of connecting a set of terminals Z using orthogonal and diagonal edges with minimum length. This problem has many applications, such as the EDA, VLSI circuit design, fault-tolerant routing in mesh-based broadcast, and Printed Circuit Board (PCB). This paper proposes an obstacle-avoiding 4/8/10/26-directional heuristic algorithm for this problem based on the Areibi's concept, Higher Geometry Maze Routing, and Sollin's minimal spanning tree algorithm. The major contributions of this paper are (1) our work is the first report for the octilinear SMTs in the multidimensional environments, (2) we provide an optimal point-to-point routing without any refinement, and (3) the proposed algorithm has higher adaptability to deal with any irregular environment, and can be extended to the λ-geometry without any extra work, where λ = 2, 4, 8 and ∞ corresponding to rectilinear, 45 • , 22.5 • and Euclidean geometries respectively. INDEX TERMS Higher geometry maze routing, octilinear, rectilinear, Steiner tree.

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Section: B Experimental Results and Observationsmentioning

confidence: 88%

Section: B Experimental Results and Observationsmentioning

confidence: 88%

Section: B Experimental Results and Observationsmentioning

confidence: 99%

Section: Steiner Problem and Current Related Work A The Steinermentioning

confidence: 99%

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An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments

2020

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“…For example, because of structural differences, digital circuits and analog circuits can hardly detect the HT of both in the same way. (4) With the diversification of IC design concepts [ 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ] and the continuous expansion of scale, the HT of corresponding chip platform will become more complicated and its attack patterns will also be diversified.…”

Section: Introductionmentioning

confidence: 99%

Hardware Trojans in Chips: A Survey for Detection and Prevention

Dong

Liu

et al. 2020

Sensors

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Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.

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