Porous silicon reorganization: Influence on the structure, surface roughness and strain

Milenkovic, Nena; Drießen, M.; Weiss, Charlotte; Janz, S.

doi:10.1016/j.jcrysgro.2015.09.025

Cited by 22 publications

(9 citation statements)

References 13 publications

(22 reference statements)

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“…Figure 9 shows the XRD pattern of pristine SiNWs and sintered SiNWs at various sintering temperatures. The highlighted circle indicates the formation of strain due to stress developed on the sidewalls of NWs array 39 , 40 . Out-of-plane lattice expansion in the pristine NWs produces tensile out-of-plane strain on the NWs, as shown in Fig.…”

Section: Discussionmentioning

confidence: 99%

Removal of Ag remanence and improvement in structural attributes of silicon nanowires array via sintering

Kale

Sahoo

2021

Sci Rep

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Metal-assisted chemical etching (MACE) is popular due to the large-area fabrication of silicon nanowires (SiNWs) exhibiting a high aspect ratio at a low cost. The remanence of metal, i.e., silver nanoparticles (AgNPs) used in the MACE, deteriorates the device (especially solar cell) performance by acting as a defect center. The superhydrophobic behavior of nanowires (NWs) array prohibits any liquid-based solution (i.e., thorough cleaning with HNO3 solution) from removing the AgNPs. Thermal treatment of NWs is an alternative approach to reduce the Ag remanence. Sintering temperature variation is chosen between the melting temperature of bulk-Ag (962 °C) and bulk-Si (1412 °C) to reduce the Ag particles and improve the crystallinity of the NWs. The melting point of NWs decreases due to surface melting that restricts the sintering temperature to 1200 °C. The minimum sintering temperature is set to 1000 °C to eradicate the Ag remanence. The SEM–EDS analysis is carried out to quantify the reduction in Ag remanence in the sintered NWs array. The XRD analysis is performed to study the oxides (SiO and Ag2O) formed in the NWs array due to the trace oxygen level in the furnace. The TG-DSC characterization is carried out to know the critical sintering temperature at which remanence of AgNPs removes without forming any oxides. The Raman analysis is studied to determine the crystallinity, strain, and size of Si nanocrystals (SiNCs) formed on the NWs surface due to sidewalls etching. An optimized polynomial equation is derived to find the SiNCs size for various sintering temperatures.

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Section: Discussionmentioning

confidence: 99%

Removal of Ag remanence and improvement in structural attributes of silicon nanowires array via sintering

Kale

Sahoo

2021

Sci Rep

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“…[11] Based on our earlier observations, we systematically optimize the efficiency potential on state-of-the-art epitaxially grown silicon wafers by e.g., finding the best suited base resistivity and thickness in this contribution. [8] As the base resistivity (i.e., the doping concentration) has a strong influence on the cell performance which in turn depends on the material specific impurity mix, it is of high importance to understand the still limiting mix of bulk defects in epitaxially grown material. [12,13] Despite of some research on epitaxially grown p-type Si in direct comparison to epitaxially grown n-type Si, the impurity mix in p-type epitaxial silicon is neither investigated nor known yet.…”

Section: Introductionmentioning

confidence: 99%

“…The influence of the properties of the porous silicon detachment layer on EpiWafer's quality has been studied by various groups and is still ongoing. [7][8][9] Again for EpiWafers, the influence of the substrate itself as well as of the reactor for epitaxial growth has been discussed. [10] In this contribution, we demonstrate in turn that EpiRef wafers are well suited for high-efficiency TOPCoRE cells which have just recently shown efficiencies up to 26% for float-zone material.…”

Section: Introductionmentioning

confidence: 99%

Epitaxially Grown p‐type Silicon Wafers Ready for Cell Efficiencies Exceeding 25%

et al. 2022

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Combining the advantages of a high‐efficiency solar cell concept and a low carbon footprint base material is a promising approach for highly efficient, sustainable, and cost‐effective solar cells. In this work, we investigate the suitability of epitaxially grown p‐type silicon wafers for solar cells with tunnel oxide passivating contact rear emitter. As a first proof of principle, an efficiency limiting bulk recombination analysis of epitaxially grown p‐type silicon wafers deposited on high quality substrates (EpiRef) unveils promising cell efficiency potentials exceeding 25% for three different base resistivities of 3, 14, and 100 Ω cm. To understand the remaining limitations in detail, concentrations of metastable defects Fei, CrB and BO are assessed by lifetime‐calibrated photoluminescence imaging and their impact on the overall recombination is evaluated. The EpiRef wafers’ efficiency potential is tracked along the solar cell fabrication process to quantify the impact of high temperature treatments on the material quality. We observe large areas with few structural defects on the wafer featuring lifetimes exceeding 10 ms and an efficiency potential of 25.8% even after exposing the wafer to a thermal oxidation at 1050 °C.

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“…Milenkovic et al . 30 reported that based on an X-ray diffraction rocking curve, a 950 °C annealing treatment can shift the peak of as-etched porous silicon to higher diffraction angles, changing a tensile out-of-plane strain into a compressive out-of-plane strain. Because tensile strain usually increases with increasing porosity and mean pore radius, this finding indicates that the pores become much smaller if the strain is changed from tensile to compressive.…”

Section: Introductionmentioning

confidence: 99%

Annihilating Pores in the Desired Layer of a Porous Silicon Bilayer with Different Porosities for Layer Transfer

Chiang

Lee

2019

Sci Rep

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A silicon layer that is tens of micrometers thick on a handle substrate is desired for applications involving power devices, microelectromechanical systems (MEMS), highly efficient silicon solar cells (<50 µm), etc. In general, if the initial silicon layer obtained from the layer transfer process using the etch-stop or ion-cut techniques, which may provide very accurate thickness control, is too thin, then additional epitaxial growth is required to increase the thickness of the silicon layer. However, epitaxial growth under strict predeposition conditions is a time-consuming and expensive process. On the other hand, producing porous silicon via anodization in a hydrofluoric acid solution offers an efficient way to control the dimensions of the generated pores directly on the nano- or macroscale via the current density. When sintering the porous layer via high-temperature argon annealing, the porosity of the porous layer determines whether this porous layer can serve as a device layer or a separation layer. In addition, it is clearly easier to create a transferred layer ten of micrometers thick via anodization than by ion implantation and/or epitaxial deposition.

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Porous silicon reorganization: Influence on the structure, surface roughness and strain

Cited by 22 publications

References 13 publications

Removal of Ag remanence and improvement in structural attributes of silicon nanowires array via sintering

Removal of Ag remanence and improvement in structural attributes of silicon nanowires array via sintering

Epitaxially Grown p‐type Silicon Wafers Ready for Cell Efficiencies Exceeding 25%

Annihilating Pores in the Desired Layer of a Porous Silicon Bilayer with Different Porosities for Layer Transfer

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