Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks

Ho, Nhut-Minh; Nguyen, Duy-Thanh; Silva, Himeshi De; Gustafson, John L.; Wong, Weng-Fai; Chang, Ik Joon

doi:10.23919/date51398.2021.9473933

Cited by 13 publications

(1 citation statement)

References 6 publications

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“…Posit [1] is regarded as a drop-in replacement for the conventional IEEE-754 floating-point (FP) format [2] due to its better trade-off between dynamic range and accuracy [3]. Many fields have benefited from the posit data format since its emergence, including weather forecasts [4], graph processing [5] and deep learning [6]. For deep learning applications, in particular, prior arts have optimized deep neural networks (DNNs) using posit data types for efficient inference [7] [8] and training [9] [10].…”

Section: Introductionmentioning

confidence: 99%

PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications

Li¹,

Fang²,

Wang³

2023

Preprint

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Posit has been a promising alternative to the IEEE-754 floating point format for deep learning applications due to its better trade-off between dynamic range and accuracy. However, hardware implementation of posit arithmetic requires further exploration, especially for the dot-product operations dominated in deep neural networks (DNNs). It has been implemented by either the combination of multipliers and an adder tree or cascaded fused multiply-add units, leading to poor computational efficiency and excessive hardware overhead. To address this issue, we propose an open-source posit dot-product unit, namely PDPU, that facilitates resource-efficient and high-throughput dotproduct hardware implementation. PDPU not only features the fused and mixed-precision architecture that eliminates redundant latency and hardware resources, but also has a fine-grained 6-stage pipeline, improving computational efficiency. A configurable PDPU generator is further developed to meet the diverse needs of various DNNs for computational accuracy. Experimental results evaluated under the 28nm CMOS process show that PDPU reduces area, latency, and power by up to 43%, 64%, and 70%, respectively, compared to the existing implementations. Hence, PDPU has great potential as the computing core of posit-based accelerators for deep learning applications.

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