Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs

Tanakamaru, Shuhei; Fukuda, Mayumi; Higuchi, Kazuhide; Esumi, Atsushi; Ito, Mitsuyoshi; Li, Kai; Takeuchi, Ken

doi:10.1016/j.sse.2010.11.025

Cited by 7 publications

(2 citation statements)

References 7 publications

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“…SSD device vendors or SSD standards generally specify their ABER. For example, the uncorrectable bit error rate under typical workload execution should be less than 10 −15 [24].…”

Section: Solution: Conditional Remapping Invocation Methodsmentioning

confidence: 99%

CRIM: Conditional Remapping to Improve the Reliability of Solid-State Drives with Minimizing Lifetime Loss

Kim

Park

Hong

2018

Scientific Programming

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Solid-state drive (SSD) becomes popular as the main storage device. However, over time, the reliability of SSD degrades due to bit errors, which poses a serious issue. The periodic remapping (PR) has been suggested to overcome the issue, but it still has a critical weakness as PR increases lifetime loss. Therefore, we propose the conditional remapping invocation method (CRIM) to sustain reliability without lifetime loss. CRIM uses a probability-based threshold to determine the condition of invoking remapping operation. We evaluate the effectiveness of CRIM using the real workload trace data. In our experiments, we show that CRIM can extend a lifetime of SSD more than PR by up to 12.6% to 17.9% of 5-year warranty time. In addition, we show that CRIM can reduce the bit error probability of SSD by up to 73 times in terms of typical bit error rate in comparison with PR.

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“…SSD device vendors or SSD standards generally specify their ABER. For example, the uncorrectable bit error rate under typical workload execution should be less than 10 −15 [24].…”

Section: Solution: Conditional Remapping Invocation Methodsmentioning

confidence: 99%

CRIM: Conditional Remapping to Improve the Reliability of Solid-State Drives with Minimizing Lifetime Loss

Kim

Park

Hong

2018

Scientific Programming

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“…The larger user data size improves BCH ECC strength. 29) Figure 7(a) shows an architecture of BCH ECC decoder. BCH decoding operation induces delay by the series of syndrome generation, Barlekamp-Massey (BM), and Chein search.…”

Section: Error-correcting Codes For Scm and Nand Flashmentioning

confidence: 99%

Analysis on applicable error-correcting code strength of storage class memory and NAND flash in hybrid storage

Matsui¹,

Kinoshita²,

Takeuchi³

2018

Jpn. J. Appl. Phys.

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A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.

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AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDs

Zhan

Wang

Feng

et al. 2020

2020 IEEE 38th International Conference on Computer Design (ICCD)

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Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs

Cited by 7 publications

References 7 publications

CRIM: Conditional Remapping to Improve the Reliability of Solid-State Drives with Minimizing Lifetime Loss

CRIM: Conditional Remapping to Improve the Reliability of Solid-State Drives with Minimizing Lifetime Loss

Analysis on applicable error-correcting code strength of storage class memory and NAND flash in hybrid storage

AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDs

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