Post-processing and performance analysis of BEOL integrated MEMS pressure sensor capacitors in 8-metal 130nm CMOS

Sundararajan, Ananiah Durai; Hasan, S. M. Rezaul

doi:10.1016/j.mee.2014.02.035

Cited by 3 publications

(5 citation statements)

References 15 publications

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“…Moreover, the sub-micron level sensing gap can be achieved through this approach to enhance the sensitivity of the capacitive pressure sensor. As indicated in figure 11, the sealant is used to seal these pressure sensors, and different films, for example parylene, metals or other materials, can be deposited [87][88][89][90][91][92][93][94][95][96]. Note that the vacuum condition of the sealed chamber is determined by the pressure of film deposition chamber (for example: the chamber pressure is near 10 Pa (∼75 mTorr) if sealed by the parylene [87][88][89]) and the outgassing from chamber walls during subsequent processes.…”

Section: Capacitive Pressure Sensorsmentioning

confidence: 99%

“…As shown in figures 13(a) and (b), pressure sensor fabricated from the SMIC 0.18 µm CMOS process was sealed using evaporated aluminum [93]. The deformable structure of the pressure sensor was also The schematic illustrations of the absolute pressure sensor sealed by depositing various materials: (a) Al [93], (b) TEOS [94], (c) silicon dioxide [95] and fluorosilicate glass [96].…”

Section: Etching Hole Released Diaphragm Deposited Sealantmentioning

confidence: 99%

“…Furthermore, as shown in figure 13(b), the sensor was implemented using the in-house CMOS and post-CMOS processes, and the chamber was sealed using deposited tetraethyl orthosilicate (TEOS) oxide with a pressure of 0.4-0.5 Torr [94]. Similarly, using the CMOS BEOL to define the pressure sensor structure [95,96], have demonstrated the sealing of the reference chamber using materials such as silicon dioxide (with a chamber pressure of 6 mTorr) and fluorosilicate glass (with a chamber pressure of 0.5 Torr), both by the PECVD (plasma-enhanced chemical vapor deposition) process, respectively shown in figure 13(c) and (d). The CMOS processes used to define the pressure sensor structure [95,96] were respectively the GLOBAL-FOUNDRIES (GlobalFoundries Inc., USA) 0.18 µm CMOS process, and the 8 M 130 nm IBM (International Business Machines Corp., USA) CMOS process.…”

Section: Etching Hole Released Diaphragm Deposited Sealantmentioning

confidence: 99%

See 2 more Smart Citations

CMOS-MEMS technologies for the applications of environment sensors and environment sensing hubs

Lee

Hsieh

Lin

et al. 2021

J. Micromech. Microeng.

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The booming growth in environmental conditions sensing and monitoring pushes the need of inexpensive environment sensors with small size and low power consumption. The outbreak of COVID-19 further increases the need for fast monitoring of environment conditions. The micro-electrical-mechanical-systems (MEMS) technologies are considered as promising solutions to realize the required environment sensors. The mature complementary metal-oxide-semiconductor (CMOS) process platforms available in many foundries can be extended to fabricate MEMS sensors to offer the advantage of relatively easier commercialization. Moreover, by leveraging the characteristics of CMOS process platforms, the integration of multiple sensors and sensing circuits to form a compact sensing system can also be achieved. This review paper will focus on introducing the miniaturized environmental sensing devices implemented and integrated using the CMOS-MEMS technologies. In general, the CMOS chips for environment sensing are firstly fabricated using the foundry-available CMOS processes, and then the post-CMOS micromachining processes are performed to implement the CMOS-MEMS environment sensors. This paper respectively reviews five different environment sensors (including the infrared, pressure (barometer), humidity/temperature, and gas sensors) using the CMOS-based MEMS technologies. The advantages and design concerns of sensors fabricated by different CMOS and post-CMOS processes are introduced and discussed. Moreover, the CMOS-MEMS environment sensing hub implemented through the monolithic integration of multiple environment sensors is also introduced.

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Section: Capacitive Pressure Sensorsmentioning

confidence: 99%

Section: Etching Hole Released Diaphragm Deposited Sealantmentioning

confidence: 99%

Section: Etching Hole Released Diaphragm Deposited Sealantmentioning

confidence: 99%

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CMOS-MEMS technologies for the applications of environment sensors and environment sensing hubs

Lee

Hsieh

Lin

et al. 2021

J. Micromech. Microeng.

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“…The high refractive index and optical transparency 7 of high-k oxides also makes them of interest in waveguide and optical coating applications. [418][419][420] High-k oxides are even of interest for various gas pressure 421 and chemical sensors 53,[422][423][424] applications due to the significant ionic conductivity and defect chemistry exhibited by materials such as ZnO, TiO 2 , ZrO 2 , and HfO 2 . 425 The role of high-k materials has also continued to expand in more traditional logic and memory device applications.…”

Section: High-k and Low-k Dielectrics: What Was Old Becomes New Againmentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

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High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

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“…The minimum achievable resolution with ×5 lens is 8 μm and with ×40 lens it is 1 μm. 11 Photoresist (PR) is a light-sensitive material, which reacts with UV light. This reaction changes the chemical structure of PR and makes it soluble or insoluble depending upon the nature of the resist.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of back contacts using laser writer and photolithography for inscribing textured solar cells

2015

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Semiconductor fabrication process begins with photolithography. Preparing a photo mask is the key process step in photolithography. The photo mask was fabricated by inscribing patterns directly onto a soda lime glass with the help of a laser beam, as it is easily controllable. Laser writer LW405-A was used for preparing the mask in this study. Exposure wavelength of 405 nm was used, with which 1.2 μm feature size can be written in direct write-mode over the soda lime glass plate. The advantage of using the fabricated mask is that it can be used to design back contacts for thin film Photovoltaic (PV) solar cells. To investigate the process capability of LW405-A, same pattern with different line widths was written on soda lime glass samples at different writing speeds. The pattern was inscribed without proximity effect and stitching errors, which was characterized using optical microscope and field emission scanning electron microscope (FE-SEM). It was proven that writing speed of a mask-writer is decided according to the intended feature size and line width. As the writing speed increases, the edges of the patterns become rougher due to uneven scattering of the laser beam. From the fabricated mask, the solar cell can be developed embedding both the contacts at the bottom layer, to increase the absorption of solar radiation on the top surface effectively by increasing light absorption area.

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Post-processing and performance analysis of BEOL integrated MEMS pressure sensor capacitors in 8-metal 130nm CMOS

Cited by 3 publications

References 15 publications

CMOS-MEMS technologies for the applications of environment sensors and environment sensing hubs

CMOS-MEMS technologies for the applications of environment sensors and environment sensing hubs

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Fabrication of back contacts using laser writer and photolithography for inscribing textured solar cells

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