Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing

Gregg, Jessica; Chen, T.W.

doi:10.1109/tvlsi.2007.893626

Cited by 32 publications

(22 citation statements)

References 16 publications

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“…For example, Nabaa et al [23] proposed the use of ABB through the use of the new FPGA architecture that includes an additional characterizer circuit to reduce the leakage energy by 3 times. Gregg et al [10] proposed using ABB to compensate for the process variation and improve delay and leakage. Chen et al [6] compare the effectiveness of adaptive supply voltage (ASV) and ABB.…”

Section: Adaptive Body Biasmentioning

confidence: 99%

Energy attacks and defense techniques for wireless systems

Wei

Ahnn

Potkonjak

2013

Proceedings of the Sixth ACM Conference on Security and Privacy in Wireless and Mobile Networks

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This paper addresses the energy attacks towards wireless systems, where energy is the most critical constraint to lifetime and reliability. We for the first time propose a hardwarebased energy attack, namely energy hardware Trojans (HTs), which can be well hidden in the wireless systems and trigger ultra-high energy increases at runtime. Then, we develop a non-destructive HT detection approach to identify the energy attack by remotely sampling the power profiles of the system and characterizing the gate-level temperatures. Our evaluation results on ISCAS benchmarks indicate the effectiveness of the proposed energy attacks and defense techniques.

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Section: Adaptive Body Biasmentioning

confidence: 99%

Energy attacks and defense techniques for wireless systems

Wei

Ahnn

Potkonjak

2013

Proceedings of the Sixth ACM Conference on Security and Privacy in Wireless and Mobile Networks

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“…Recently, individual well-adaptive body biasing schemes of locally generated body biases have been proposed providing fine-grained control [1]. The decision of how to group the devices is made at design time, but the tuning decision occurs after fabrication during test.…”

Section: Related Workmentioning

confidence: 99%

“…Otherwise, simply meeting timing with VI is no better than scaling the global voltage with respect to the worst-case critical path in each chip to meet timing. Figure 11 presents boxplots 1 for the 1000 CMP chips with VI (VDDH = 1.2V, VDDL = 0.9V) across a number of different chip frequency targets, but again presented in terms of delay. The x-axis is normalized to the nominal, no variations delay, and the y-axis is normalized to the nominal voltage chip energy (nominal VDD = 1.05V).…”

Section: Impact Of Variationsmentioning

confidence: 99%

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Evaluation of voltage interpolation to address process variations

Brownell

Wei

Brooks

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-Post-fabrication tuning provides a promising design approach to mitigate the performance and power overheads of process variation in advanced fabrication technologies. This paper explores design considerations and VLSI-CAD support for a recently proposed postfabrication tuning knob called voltage interpolation. The paper discusses design tradeoffs between circuit tuning range and static power overheads that can be performed within the synthesis flow of the design process. The paper explores the scheme for a 64-core chip-multiprocessor machine using industrial-grade design blocks and shows that the scheme can be used to mitigate overhead arising from random and correlated within-die process variations. The analysis shows that the scheme can match the nominal delay target with a 10% power cost, or for the same power budget, incur only a 9% delay overhead after variations.

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“…Recent proposals [3], [4], [5] have suggested that post-silicon adaptivity can be used to improve SRAM yield and also reduce power consumption. Postsilicon adaptivity involves measuring leakage/latency of SRAM(s) and provide on-chip mechanisms to enforce circuit-level optimizations based on these measurements.…”

Section: Introductionmentioning

confidence: 99%

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Ganapathy

Canal

González

et al. 2011

2011 IEEE 29th International Conference on Computer Design (ICCD)

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Abstract-In this paper, we propose a dynamically tunable fine-grain body biasing mechanism to reduce active & standby leakage power in caches under process variations. Front body biasing (FBB) is employed for active sub-arrays to speed up accesses while inactive sub-arrays are reverse body biased (RBB) to reduce standby leakage power. Cache subarrays are classified based on run-time leakage and latency distributions and applied bias voltage is updated to account for these changes. This ensures that under all scenarios, the cache will consume the lowest leakage power for the target access latency computed at design-time. The backbone of the hardware used for classification is the 3T1D DRAM cell embedded into conventional 6T based memory. By measuring the access and retention time of the 3T1D cell, we show that it is possible to classify cache arrays based on run-time latency/leakage measurements. The tremendous increase in energy in active mode by forward biasing (to meet latency requirements) is compensated by reverse biasing inactive arrays. Our technique reduces leakage energy consumption and access latency of the cache on average by 20% & 18% respectively when compared to other state-of-the-art proposals. Finally we show that our technique will improve parametric yield by a maximum of 38% for worst-case scenario.

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Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing

Cited by 32 publications

References 16 publications

Energy attacks and defense techniques for wireless systems

Energy attacks and defense techniques for wireless systems

Evaluation of voltage interpolation to address process variations

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

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