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1.NBSTRACTAn analysis of the main contributors to the quality aidcost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus ,Surface Mount Technology (SMT) solder defect rate, component functional defect rate and test coverage. A new Yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on A S K S is given.

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Radiation-induced soft errors on large-scale integratedcircuits are becoming increasingly problematic as device sizes are scaled down, operating voltages are reduced, and node capacitances shrink. Therefore, chip reliability has become a big issue in modern VLSI design and the importance of detecting soft error in combinational logic circuits has been recognized. In this paper a method incorporating two error detecting methods, parity check and shadow latch, is presented. The results show that the proposed method combines the best of both previously proposed methods and achieves the soft error rate reduction of 70% with 50% cost overhead for random logic blocks, providing a better cost return for using either method along.