Defects, fault coverage, yield and cost, in board manufacturing

Tegethoff, M.M.V.; Chen, T.W.

doi:10.1109/test.1994.527997

Cited by 15 publications

(3 citation statements)

References 9 publications

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“…Using a nonlinear regression analysis technique, (5) gives the relationship between test cost and fault coverage that was assumed in Abdir and is used in the RCGAs optimization of the MCM assembly process, A MCM manufacturing and test model [15]. Fig.…”

Section: Optimization Of Fault Coverage In the MCM Assembly Process Flowmentioning

confidence: 99%

Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly

Shi

Sandborn

2006

J Electron Test

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Abstract. In this paper, an optimization methodology is used to select the locations and characteristics of test, diagnosis and rework operations in electronic systems assembly processes. Real-coded genetic algorithms are used to perform a multi-variable optimization that minimizes the yielded cost of products resulting from an assembly process that includes test/diagnosis/rework operations characterized by costs, yields fault coverage, and rework attempts. A general complex process flow is analyzed using the algorithms proposed in this paper, and a multichip module assembly process flow is used to demonstrate that the methodology can identify optimum test and rework solutions that result in a reduction in yielded cost.

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Section: Optimization Of Fault Coverage In the MCM Assembly Process Flowmentioning

confidence: 99%

Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly

Shi

Sandborn

2006

J Electron Test

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“…PCB Assembly Defects. Assembly defects in PCB technology may lead to the rotation of a component, to a reversed polarity or to the exchange of a component by another [14] as illustrated on the Fig. 4.…”

Section: Analog Faultsmentioning

confidence: 99%

Fault simulation for mixed-signal systems

Caunegre

Abraham

1996

J Electron Test

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Abstract. This paper proposes a solution to achieve the global fault simulation for mixed-signal systems. Fault models for analog defects are introduced. Short-circuit defects, involving two digital nodes or involving a digital and an analog node, are also supported. Short-circuit modelling is achieved by a local analog simulation and by means of new mixed-signal models suggested for CMOS devices. Using a commercially available mixed-signal simulator, we built surrounding tools to automate the fault simulation. By processing the circuit description files, they allow generating and reducing a fault list and controlling the fault simulation. Simulation results are also processed in order to produce an exhaustivity report and a selection of the best test vectors.

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“…There are several existing test/rework models that are applicable to process modeling and process-flow based cost analyses for electronic systems. Basic models, (e.g., Dislis et al 1993, Tegethoff and Chen 1994, Scheffler et al 1998 account for test fault coverage and single rework attempts (diagnosis is combined with rework and not explicitly treated). These models also assume that the application of the test does not contribute defects to the product, and that the test produces no false positives.…”

Section: Introductionmentioning

confidence: 99%

Modeling Test, Diagnosis, and Rework Operations and Optimizing Their Location in General Manufacturing Processes

Shi

Sandborn

2003

Volume 3a: 8th Design for Manufacturing Conference

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This paper presents a test, diagnosis, and rework analysis model for use in manufacturing process modeling. The approach includes a model of functional test operations characterized by fault coverage, false positives, and defects introduced in test, in addition to rework and diagnosis (diagnostic test) operations that have variable success rates and their own defect introduction mechanisms. The model accommodates multiple rework attempts on a product instance. The model is applied within a framework for optimizing the location(s) and characteristics (fault coverage/test cost, rework success rate/rework cost) of Test/Diagnosis/Rework (TDR) operations in a general manufacturing process. A new search algorithm called Waiting Sequence Search (WSS) is applied to traverse a general process flow to perform the cumulative calculation of a yielded cost objective function. Real-Coded Genetic Algorithms (RCGAs) are used to perform a multi-objective optimization that minimizes yielded cost. An example of a general complex process flow is used to demonstrate the feasibility of the algorithm.

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Defects, fault coverage, yield and cost, in board manufacturing

Cited by 15 publications

References 9 publications

Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly

Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly

Fault simulation for mixed-signal systems

Modeling Test, Diagnosis, and Rework Operations and Optimizing Their Location in General Manufacturing Processes

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