Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Matsunaga,; Kimura,

doi:10.1109/islped.2011.5993639

Cited by 15 publications

(7 citation statements)

References 8 publications

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“…They note that both Altera and Xilinx have efficient ternary adders, so they use GPCs to reduce the matrix to three rows. Other work on GPCs that is based on work by Parandeh-Afshar et al presents incremental improvements or additional applications for GPCs [13][14][15]17,20]. Kumm and Zipf present two novel GPCs, (6,0,6;5) and (1,3,2,5;5), that are specific to and optimized for Xilinx FPGAs [19].…”

Section: Related Work: Generalized Parallel Countersmentioning

confidence: 99%

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Walters

2016

Computers

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Abstract:Multiplication is the dominant operation for many applications implemented on field-programmable gate arrays (FPGAs). Although most current FPGA families have embedded hard multipliers, soft multipliers using lookup tables (LUTs) in the logic fabric remain important. This paper presents a novel two-operand addition circuit (patent pending) that combines radix-4 partial-product generation with addition and shows how it can be used to implement two's-complement array multipliers. The circuit is specific to modern Xilinx FPGAs that are based on a 6-input LUT architecture. Proposed pipelined multipliers use 42%-52% fewer LUTs, and some versions can be clocked up to 23% faster than delay-optimized LogiCORE IP multipliers. This allows 1.72-2.10-times as many multipliers to be implemented in the same logic fabric and potentially offers 1.86-2.58-times the throughput by increasing the clock frequency.

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Section: Related Work: Generalized Parallel Countersmentioning

confidence: 99%

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Walters

2016

Computers

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“…Heuristics [179] and ILP formulations [180] are proposed for optimizing the delay of compressor trees while also considering the FPGA carry chain for the implementation of GPC [181]. ILP formulations are also proposed for reduced power consumption by reducing not only the depth but also the number of GPCs [182,183] while efforts to optimize the number of resources for high throughput pipelined designs have been proposed in [184]. In [173], authors present a technique to completely avoid the compressor trees by merging the Booth recoding with the ripple-carry summation of the partial products in a single stage of LUTs, fast carry chains and flip flops.…”

Section: Fpgas For Dsp Implementationmentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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“…Burhan Khurshid is with the Department of Computer Science and Engineering, National Institute of Technology Srinagar, Jammu and Kashmir, India, 190006 (phone: +91-9797875163; e-mail: burhan_07phd12@nitsri.net). comparable resource utilization [8,9,10,11,12,13,14]. Initial attempts in this regard were made by Parandeh-Afshar et al [8,9,10,11].…”

Section: Introductionmentioning

confidence: 99%

“…Matsunaga et al [12,14] also formulated the mapping of GPCs as an ILP with speed and power as optimization goals. Their results show a 28% reduction in GPC count when compared to [9].…”

Section: Introductionmentioning

confidence: 99%

LUT Based Generalized Parallel Counters for State - of - art FPGAs

Khurshid¹

2017

ELS

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3 1 Abstract-Generalized Parallel Counters (GPCs) are frequently used in constructing high speed compressor trees. Previous work has focused on achieving efficient mapping of GPCs on FPGAs by using a combination of general Look-up table (LUT) fabric and specialized fast carry chains. The resulting structures are purely combinational and cannot be efficiently pipelined to achieve the potential FPGA performance. In this paper, we take an alternate approach and try to eliminate the fast carry chain from the GPC structure. We present a heuristic that maps GPCs on FPGAS using only general LUT fabric. The resultant GPCs are then easily re-timed by placing registers at the fan-out nodes of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry chain from the GPC structure with the same LUT count in most of the cases. Experimental results using Xilinx Kintex-7 FPGAs show a considerable reduction in critical path and dynamic power dissipation with same area utilization in most of the cases.

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Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Cited by 15 publications

References 8 publications

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Techniques for Efficient Implementation of FIR and Particle Filtering

LUT Based Generalized Parallel Counters for State - of - art FPGAs

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