Power‐aware computing

Ezzatti, Pablo; Quintana–Ort́ı, Enrique S.; Remón, Alfredo; Saak, Jens

doi:10.1002/cpe.5034

Cited by 14 publications

(6 citation statements)

References 9 publications

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“…The large computing infrastructures are becoming more and more limited by power/energy constraints, so it is understandable why the energy efficiency of HPC parallel workloads become a focus of attention in recent times [12]. Beside the trend of energy reduction achieved through reengineering the hardware, we can observe another one with an excellent potential for energy savings that is realized by transforming and completely rethinking the algorithms and software dedicated for HPC platforms [13].…”

Section: Related Workmentioning

confidence: 99%

Correlation of Performance Optimizations and Energy Consumption for Stencil-Based Application on Intel Xeon Scalable Processors

Szustak

Wyrzykowski

Olas

et al. 2020

IEEE Trans. Parallel Distrib. Syst.

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This article provides a comprehensive study of the impact of performance optimizations on the energy efficiency of a real-world CFD application called MPDATA, as well as an insightful analysis of performance-energy interaction of these optimizations with the underlying hardware that represents the first generation of Intel Xeon Scalable processors. Considering the MPDATA iterative application as a use case, we explore the fundamentals of energy and performance analysis for a memory-bound application when exposed to a set of optimization steps that increase the application performance, by improving the operational intensity of code and utilizing resources more efficiently. It is shown that for memory-bound applications, optimizing toward high performance could be a powerful strategy for improving the energy efficiency as well. In fact, for the considered performance optimizations, the energy gain is correlated with the performance gain but with varying degrees. As a result, these optimizations allow improving both performance and energy consumption radically, up to about 10.9 and 8.8 times, respectively. The impact of the Intel AVX-512 SIMD extension on the energy consumption and performance is demonstrated. Also, we discover limitations on the usability of CPU frequency scaling as a tool for balancing energy savings with admissible performance losses.

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Section: Related Workmentioning

confidence: 99%

Correlation of Performance Optimizations and Energy Consumption for Stencil-Based Application on Intel Xeon Scalable Processors

Szustak

Wyrzykowski

Olas

et al. 2020

IEEE Trans. Parallel Distrib. Syst.

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“…A great potential for energy savings can be realized by transforming and completely rethinking the system architectures and current applications running on present platforms. But this type of redesign relies on a highly interdisciplinary expertise coupling the knowledge of the domain, of the applicative framework together with a good knowledge of the hardware …”

Section: Themes Of This Special Issuementioning

confidence: 99%

Latest advances in parallel, distributed, and network‐based processing

Merelli

Lió

Kotenko

et al. 2020

Concurrency and Computation

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This editorial introduces the articles selected for the special issue concerning the International Conferences on Parallel, Distributed, and Network-Based Processing, which provided insights related to the efficient exploitation of parallel and distributed architectures, including power-aware computing, application scheduling, and application development for GPUs. K E Y W O R D SComputing, gpu computing, network-based computing, parallel Computing

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“…Thus, researchers should explore effective alternatives to these emerging architectural problems. The challenge arises from the fact that this form of redesign necessitates a high level of integrative skill, combining mathematical modelling, computational techniques, software architecture, and hardware-aware computing [1,2].…”

Section: Introductionmentioning

confidence: 99%

Power-aware Future Computing Systems Using Machine Learning Techniques

Al-Obaidy

2024

Preprint

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<p>There is a growing demand for hardware systems that are computationally efficient and energy saving, to accelerate compute-intensive applications. These exciting challenges, such as memory access and GPU throughput, take performance, power, and resource trade-offs into account. This is especially relevant to a relatively new approach: Accelerating and running parallel computing systems using a machine learning (ML) technique. The objective of this thesis is to explore the hardware design requirements, and select appropriate choices for multi-core architectures, based on different ML, to address these challenges. This thesis contributes by developing effective hardware architectures which trade-off design objectives, by focusing on the following four distinct fields: • Utilization of low-power cache designs. The objective of this design is to use the artificial neural network (ANN) predictive model to optimize a hybrid spin-torque transfer random-access memory (STT-RAM), and static random-access memory (SRAM), for multicore chips. The simulation results demonstrate that the approach can result in significant power-aware improvement for different workloads. • Development of algorithms that facilitate power savings for three-dimensional integrated networks-on-chips (3D-NoCs) design. A novel approach was efficiently developed to predict the suitable routing algorithm based on the ANN model. A trade-off power-performance function was extracted as a target for the prediction mechanism. The obtained results show high throughput with low power consumption, and reduced thermal hotspots. • Enhance power-aware resources for general purpose graphics processing unit (GPGPU). The customized model is obtained by utilizing the available chip units for each application. The energy-delay product was adopted as the target factor for the proposed ANN model. The results show that when the GPU platform is tuned to the required resources, prediction accuracy, and power consumption are highly improved. This methodology provides more flexibility for the running application to face power challenges when using maximum hardware on the GPU systems. • To improve the performance of the 3D-NoC accelerator platform, we extended the integrated 3D-NoC based ANN simulator to support interconnection routing through adding torus topology. The simulation results for the case study concluded that the modified platform contributes towards low latency and reduced power consumption, especially with respect to high NoC dimensions.</p>

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Power‐aware computing

Cited by 14 publications

References 9 publications

Correlation of Performance Optimizations and Energy Consumption for Stencil-Based Application on Intel Xeon Scalable Processors

Correlation of Performance Optimizations and Energy Consumption for Stencil-Based Application on Intel Xeon Scalable Processors

Latest advances in parallel, distributed, and network‐based processing

Power-aware Future Computing Systems Using Machine Learning Techniques

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