Power-aware hold optimization for ASIC physical synthesis

This article discusses power consumption trends of two geometries of carbon nanotube (CNT) bundle interconnects for very large scale integration applications. Electrostatic and electrothermal field simulations of square and triangular CNT bundle interconnects were done. Two factors viz. power dissipated and peak temperature are extracted and a new figure of merit called power temperature product (PTP) is defined. The PTP is calculated for interconnect lengths ranging from 500 to 2000µm. Results show that both triangular and square CNT bundles have high power withstanding capacity. Triangular CNT bundles have higher PTP when the associate phase changes are ignored.

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Power-aware hold optimization for ASIC physical synthesis

Cited by 2 publications

References 13 publications

Linear programming-based multi-objective floorplanning optimization for system-on-chip

Linear programming-based multi-objective floorplanning optimization for system-on-chip

Perspective—Demystifying the Power Withstanding Capabilities of CNT Bundle Interconnects

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