Power-aware multi-objective evolvable hardware system on an FPGA

López, Borja Cruz; Valverde, Juan; Torre, Eduardo de la; Riesgo, Teresa

doi:10.1109/ahs.2014.6880159

Cited by 11 publications

(5 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Evolutionary algorithms (EA) are population-based metaheuristic optimization techniques inspired by biological evolution [24]. Currently, EAs are successfully applied in different fields such as arithmetic circuit design [25], the design of fault-tolerant systems [26], and power consumption optimization [27]. Genetic algorithm (GA) is one of the more widely used EAs and has been successfully applied in various digital circuit implementations [28,29].…”

Section: Evolutionary Algorithms and Evolvable Hardwarementioning

confidence: 99%

Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans Based on Evolvable Hardware

Wang

Huang

et al. 2022

Applied Sciences

View full text Add to dashboard Cite

Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.

show abstract

Section: Evolutionary Algorithms and Evolvable Hardwarementioning

confidence: 99%

Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans Based on Evolvable Hardware

Wang

Huang

et al. 2022

Applied Sciences

View full text Add to dashboard Cite

show abstract

“…An interesting area that uses evolutionary methods to exploit unconventional dynamics is that of evolvable hardware for robot control. Evolvable hardware (EHW), or evolutionary electronics [117], is the application of evolutionary search algorithms to the design of electronic circuits [24,25,41,75,76,96]. This is a field in which our group has made recent advances, namely, the first demonstration of transistor level analog electronic controllers evolved directly in hardware for non-trivial visually guided robot behaviours [40].…”

Section: Evolving Robot Controllers Directly In Analog Electronics: Exploiting the Dynamics Of An Evolvable Physical Mediummentioning

confidence: 99%

Recent advances in evolutionary and bio-inspired adaptive robotics: Exploiting embodied dynamics

et al. 2021

View full text Add to dashboard Cite

This paper explores current developments in evolutionary and bio-inspired approaches to autonomous robotics, concentrating on research from our group at the University of Sussex. These developments are discussed in the context of advances in the wider fields of adaptive and evolutionary approaches to AI and robotics, focusing on the exploitation of embodied dynamics to create behaviour. Four case studies highlight various aspects of such exploitation. The first exploits the dynamical properties of a physical electronic substrate, demonstrating for the first time how component-level analog electronic circuits can be evolved directly in hardware to act as robot controllers. The second develops novel, effective and highly parsimonious navigation methods inspired by the way insects exploit the embodied dynamics of innate behaviours. Combining biological experiments with robotic modeling, it is shown how rapid route learning can be achieved with the aid of navigation-specific visual information that is provided and exploited by the innate behaviours. The third study focuses on the exploitation of neuromechanical chaos in the generation of robust motor behaviours. It is demonstrated how chaotic dynamics can be exploited to power a goal-driven search for desired motor behaviours in embodied systems using a particular control architecture based around neural oscillators. The dynamics are shown to be chaotic at all levels in the system, from the neural to the embodied mechanical. The final study explores the exploitation of the dynamics of brain-body-environment interactions for efficient, agile flapping winged flight. It is shown how a multi-objective evolutionary algorithm can be used to evolved dynamical neural controllers for a simulated flapping wing robot with feathered wings. Results demonstrate robust, stable, agile flight is achieved in the face of random wind gusts by exploiting complex asymmetric dynamics partly enabled by continually changing wing and tail morphologies.

show abstract

“…Vera et al (2009) proposed a dynamically reconfigurable computing model applicable for video processing applications. López et al (2014) also considered the dynamic and PR subject when developing a power-aware multi-objective evolvable FPGA-based hardware. They measured the power consumption by an instrumentation circuit involving an ADC.…”

Section: Related Workmentioning

confidence: 99%

An analysis on power consumption and performance in runtime hardware reconfiguration

Loubach¹

2021

IJES

View full text Add to dashboard Cite

It will be more difficult to continue with Moore's law scaling in the next years without exploring new heterogeneous architectures with application-customised hardware. The expressive employment of customised accelerators, or runtime reconfigurable designs, will be required to deliver power-and performance-efficient systems. In view of recent technology advances, runtime partial reconfiguration has emerged supported by FPGA-based devices. Still, power consumption and performance are the principal concerns when devising new reconfigurable embedded systems. This paper addresses power and performance analysis of the partial reconfiguration process supported by runtime reconfigurable hardware. We introduce a heterogeneous system-on-chip FPGA-based runtime partial reconfigurable platform design along with an experimental and theoretical power consumption and performance models, which are specific to the partial reconfiguration process. The proposed design was implemented, and both experimental and theoretical power consumption and performance analyses were performed, thus providing a formal tool to the decision-making process between power consumption and performance applicable to the runtime reconfiguration phase. Results show an average accuracy of 89.76% for the power consumption model and 94.82% for the performance model.

show abstract

Power-aware multi-objective evolvable hardware system on an FPGA

Cited by 11 publications

References 17 publications

Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans Based on Evolvable Hardware

Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans Based on Evolvable Hardware

Recent advances in evolutionary and bio-inspired adaptive robotics: Exploiting embodied dynamics

An analysis on power consumption and performance in runtime hardware reconfiguration

Contact Info

Product

Resources

About