Power-Aware Online Testing of Manycore Systems in the Dark Silicon Era

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

“…In such a scenario, in order to detect the occurrence of permanent failures, especially due to the aging effects, online testing represents a viable solution to cope with the limitations of in-field test and verification process. Moreover, since such architectures are usually not provided with specific Built-in-Self-Testing (BIST) circuitry (e.g., [5]), software based self-test (SBST) has been selected as a promising solution (e.g., [3], [6]). However, two different issues have to be taken into account: 1) the considerable workload to be executed which requires strict performance levels, thus leading to the necessity of a transparent test scheduling, and 2) the necessity to consider the power consumption in testing activities, thus leading to a power-aware testing approach [6], [7].…”

“…Moreover, since such architectures are usually not provided with specific Built-in-Self-Testing (BIST) circuitry (e.g., [5]), software based self-test (SBST) has been selected as a promising solution (e.g., [3], [6]). However, two different issues have to be taken into account: 1) the considerable workload to be executed which requires strict performance levels, thus leading to the necessity of a transparent test scheduling, and 2) the necessity to consider the power consumption in testing activities, thus leading to a power-aware testing approach [6], [7]. As a conclusion, we claim that in the scenario of the dark silicon era there is the quest for a power-aware test scheduling approach to detect at runtime permanent faults occurring in many-core architectures while not degrading the overall system performance.…”

“…The main contributions of this paper, which is major extension of our recent work published in [6], are: An enhanced power-aware online test scheduling method with explicit consideration of limited power budgets in many-core systems using runtime application mapping. An efficient test scheduling method for testing the cores in different voltage-frequency settings.…”

“…An efficient test scheduling method for testing the cores in different voltage-frequency settings. Extending the test criticality metric used in [6] with a lifetime reliability estimation to achieve accurate fault occurrence probability as a priority to test the cores, and to balance the regularity of the test according to the aging status of the cores. Modeling and evaluation of a many-core system using various current and future technology nodes (32, 22, and 16 nm) for different die area budgets to demonstrate the efficiency of the proposed approach in the dark silicon era.…”

An improved scheme for pre-computed patterns in core-based SoC architecture

“…A disadvantage of data compression for test is need of an ATE and the low diagnosis capability [9] [23]. Many works use built-in self-test (BIST) solutions [12] [21][22] where either pseudo-random test patterns (PRTPs) and pre-computed test patterns (or deterministic test patterns) are stored in system memory. In terms of TAT and fault coverage, deterministic test patterns tend to be more effective than PRTPs [9].…”