Power aware page allocation

Abstract

One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that p ower these mobile devic es. Memory is a particularly important tar get for e orts to improve energy e ciency. Memory technolo gy is becoming available that o ers power management features such as the ability to put individual chips in any one of several di erent power modes. In this paper we explor e the interaction of page plac ement with static and dynamic har dware p olicies to exploit these emer ginghardwar efeatures. In p articular, we c onsider p age allo cation p olicies that c an be employed b y an informed operating system to complement the hardware power management strategies. We perform experiments using two complementary simulation envir onments: a tracedriven simulator with workload traces that are r epresentative of mobile computing and an execution-driven simulator with a detaile d processor/memory model and a more memoryintensive set of benchmarks (SPEC2000). Our r esults make a compelling case for a cooperative hardwar e/softwar e approach for exploiting power-aware memory, with down to as little as 45% of the Energy Delay for the best static policy and 1% to 20% of the Ener gy Delay for a traditional fullpower memory.

Handheld System Energy Reduction by OS-Driven Refresh

“…Four DRAM sizes (4,8,16,32,64, and 128) MB, respectively, have been tested. The energy parameters of DRAM and flash memory are given in Tables 1-2.…”

“…Most studies use control algorithms that dynamically transition DRAM devices (or banks) to low power modes after they are idle for a certain threshold period of time. Lebeck, et al [8] studied DRAM power state transition policies in conjunction with software page placement policies. To improve transition decisions, they control the page allocation by working set locality.…”

Energy Efficient Configuration for QoS in Reliable Parallel Servers

“…For CMOS based variable frequency processors, power consumption is dominated by dynamic power dissipation, which is cubicly related to the supply voltage and the processing speed [2]. As for memory, it can be put into different power states with different response times [12]. For servers that employ variable frequency processors [7,8] and low power memory [17], the power consumption can be adjusted to satisfy different performance requirements.…”

Energy Characterization of Embedded Real-Time Operating Systems

“…For example Vahdat et al in [21] propose potential energy-improvements for each functionality, like interprocess communication, memory allocation, CPU scheduling, while Lebeck et al in [11] proposed a memory paging technique that aims at putting as many memory components as possible in power-down mode. Lorch and Smith in [12] suggested heuristic techniques to put the processor in lowpower states when identifying idle conditions.…”