Power balanced pipelines

Sartori, John; Ahrens, Ben; Kumar, Rakesh

doi:10.1109/hpca.2012.6169032

Cited by 17 publications

(8 citation statements)

References 9 publications

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“…It is wellknown that a pipeline consisting of equal time epochs per node (core) is optimal in parallel computational gain. Our proposed approach is similar to that given by Sartori et al [17], but differs in that we also accommodate the non-trivial time consumed during sharing of data between nodes on a pipeline. We do not assume a specialized pipeline processor platform, like the old MIPS R4000 processor, but rather a solution that is flexible enough to accommodate different inter-node data sharing semantics on any many-core processor.…”

Section: B Parallelization Through Process Pipelining: a Solution Fomentioning

confidence: 86%

Harnessing many-core processors for scalable, highly efficient, and adaptable firewall solutions

Benner

Echeverria

Onunkwo

et al. 2013

2013 International Conference on Computing, Networking and Communications (ICNC)

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Many-core processors have become the mainstay of today's computing systems. This fact and their ease of accessibility is now broadening the horizons of computational advances. In this work, we demonstrate the use of many-core processing platforms to provide scalable, efficient, and easily configurable firewall implementations on many-core processors. Our work has made possible, to the best of our knowledge, a first-known pipelined and scalable implementation of a stateful firewall on many-core processors. We discuss the results of our work and highlight areas for future considerations and improvements. Although this work focuses on the firewall as an exemplar network protection tool, the ideas developed apply to other network processing applications like network intrusion detection systems.

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Section: B Parallelization Through Process Pipelining: a Solution Fomentioning

confidence: 86%

Harnessing many-core processors for scalable, highly efficient, and adaptable firewall solutions

Benner

Echeverria

Onunkwo

et al. 2013

2013 International Conference on Computing, Networking and Communications (ICNC)

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“…Recent works have started investigating custom hardware accelerators for specific types of applications [39], [40], [41]. Prior works also consider optimizing processor pipelines for low power and energy [42], [43], [44].…”

Section: Energy Optimizationmentioning

confidence: 99%

enDebug: A hardware–software framework for automated energy debugging

Chen

Venkataramani

2016

Journal of Parallel and Distributed Computing

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Energy consumption by software applications is one of the critical issues that determine the future of multicore software development. Inefficient software has been often cited as a major reason for wasteful energy consumption in computing systems. Without adequate tools, programmers and compilers are often left to guess the regions of code to optimize, that results in frustrating and unfruitful attempts at improving application energy. In this paper, we propose enDebug, an energy debugging framework that aims to automate the process of energy debugging. It first profiles the application code for high energy consumption using a hardware-software cooperative approach. Based on the observed application energy profile, an automated recommendation system that utilizes artificial selection genetic programming is used to generate the energy optimizing program mutants while preserving functional accuracy. We demonstrate the usefulness of our framework using several Splash-2, PARSEC-1.0 and SPEC CPU2006 benchmarks, where we were able to achieve up to 7% energy savings beyond the highest compiler optimization (including profile guided optimization) settings on real-world Intel Core i7 processors.

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“…The delay constraints on microarchitectural pipeline stages can be modified in order to make them more power efficient, in a similar way to DVFS, when the performance demand of the application is relaxed [22]. In work by Bahar et al, PLB operates in response to instruction per cycle (IPC) variations within a program [21].…”

Section: A Energy Efficiency Techniques In Static Homogeneous Multicmentioning

confidence: 99%

“…They show that this PLB technique can reduce power consumption of the issue queue and execution unit by up to 23% and 13% respectively with only an average performance loss of 1% to 2% [21]. Power Balanced pipelines is a concept in which the power disparity of pipeline stages is reduced by assigning different delays to each microarchitectural pipe stage while guaranteeing a certain level of performance/throughput [22]. In a similar fashion to [21], the concept uses cycle time stealing to redistribute cycle time from low power stages to stages that can perform more efficiently if given more time.…”

Section: A Energy Efficiency Techniques In Static Homogeneous Multicmentioning

confidence: 99%

Energy Efficient Multi-Core Processing

Leech¹,

Kázmierski

2014

ELS

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Abstract-This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time minimal architectural synthesis technique to achieve greater energy and area efficiency whilst maintaining performance. The picoMIPS architecture is presented, inspired by the MIPS, as an example of a minimal and energy efficient processor. The picoMIPS is a variablearchitecture RISC microprocessor with an application-specific minimised instruction set. Each implementation will contain only the necessary datapath elements in order to maximise area efficiency. Due to the relationship between logic gate count and power consumption, energy efficiency is also maximised in the processor therefore the system is designed to perform a specific task in the most efficient processor-based form. The principles of the picoMIPS processor are illustrated with an example of the discrete cosine transform (DCT) and inverse DCT (IDCT) algorithms implemented in a multi-core context to demonstrate the concept of minimal architecture synthesis and how it can be used to produce an application specific, energy efficient processor.

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Power balanced pipelines

Cited by 17 publications

References 9 publications

Harnessing many-core processors for scalable, highly efficient, and adaptable firewall solutions

Harnessing many-core processors for scalable, highly efficient, and adaptable firewall solutions

enDebug: A hardware–software framework for automated energy debugging

Energy Efficient Multi-Core Processing

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