Power-constrained Test Scheduling for SoCs under a “no session” scheme

Abstract

This paper considers the scheduling problem of core tests in a system. Our objective is to minimize the total system test time while respecting system constraints in terms of power consumption and test resource sharing. A simple and effective scheduling heuristic is proposed based on a no sessions based scheme for better overall test time optimisation.

Power-Constrained System-on-a-Chip Test-Scheduling Using a Genetic Algorithm

“…We tested our method using various examples from the literature and compare our work to Flottes et al [4], Chakrabarty [3], and Muresan et al [9].…”

“…Larsson et al [8] presented an integrated SoC test framework by analyzing the problem of test access mechanism design along with test scheduling. Flottes et al [4] presented a heuristic approach for test scheduling for SoC with power constraints. Ravikumar et al [10] proposed a method to solve SoC test scheduling problem under the power constraints.…”

“…The example was solved in [3] using the shortest-task-first resulting in 7, 851 cycles. The total testing time obtained using our algorithm is 6, 809 Power constrained test schedule for the SoC example in [4] cycles with the schedule shown in Figure 6. The example was scheduled in 8.11 CPU seconds.…”

“…The example was later attempted by [4] with a power constraints of P max = 12 units. Muresan et al [9] test scheduled the example in 31, 000, 000 clock cycles.…”

“…However, recent techniques in test scheduling initiates tests as soon as possible. These techniques have been labeled as "sessionless" schemes [4]. An effective test scheduling approach must minimize test time while addressing resource conflicts among cores arising from the use of shared Test Access Mechanisms (TAMs) and on-chip BIST engines.…”