“…The stateful temporal logic algebra system is realizable as a neuromorphic circuit built with the seven building blocks FA , LA , D , C , M , I , R and is implementable for various hardware target architectures. It is especially suited for implementation in CMOS (Nair et al, 2020 ; Han et al, 2021 ), FPGA (Yang et al, 2021a ), and quantum-based hardware (Varadarajan, 2014 ; Gonzalez-Raya et al, 2019 ; Hamilton et al, 2019 ; Shi et al, 2019 ; Lamata, 2020 ; Marković et al, 2020 ) as nanobridge atomic switch FPGAs (Demis et al, 2015 ; Sharma et al, 2021 ) superconducting accelerators (Tzimpragos et al, 2020 ; Vakili et al, 2020 ; Feldhoff and Toepfer, 2021 ), superconducting nanowires (Toomey et al, 2019 ), nanowire networks (Diaz-Alvarez et al, 2020 ; Kendall et al, 2020 ; Kuncic et al, 2020 ; Li et al, 2020 ; Milano et al, 2020 ; Dunham et al, 2021 ; Kendall, 2021 ) and memristors (Sanz et al, 2018 ; Woźniak et al, 2020 ).…”