Power consumption reduction in MPSoCs through DFS

Rosa, Thiago Raupp da; Larrea, Vivian; Calazans, Ney; Moraes, Fernando

doi:10.1109/sbcci.2012.6344429

Cited by 21 publications

(8 citation statements)

References 13 publications

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“…For the sake of comparison, we also implement a DFS actuator using the Xilinx MMCM and resynchronization blocks [10]. The use of a DFS is justified by the impossibility to effectively scale the voltage [11]. The DFS takes 60 clock cycles to lock to the new frequency and we modeled it in the control-theoretical framework as a pure delay [10].…”

Section: Resultsmentioning

confidence: 99%

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs

Zoni

Cremona

Fornaciari

2020

IEEE Embedded Syst. Lett.

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Considering the energy-cap problem in batterypowered devices, DVFS and power gating represent the defacto state-of-the-art actuators. However, the limited margin available to reduce the operating voltage, the impossibility to massively integrate such actuators on-chip. together with their actuation latency force a revision of such design methodologies. We present an all-digital architecture and a design methodology that can effectively manage the energy-cap problem for CPUs and accelerators. Two quality metrics are put forward to capture the performance loss and the energy budget violations. We employed a vector processor supporting 4 hardware threads as representative usecase. Results show an average performance loss and energy cap violations limited to 2.9% and 3.8%, respectively. Compared to solutions employing the DFS actuator, our alldigital architecture improves the energy-cap violations by 3x while maintaining a similar performance loss.Index Terms-Energy-constrained design, low power, digital design, RTL design, multi-core, power management.

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Section: Resultsmentioning

confidence: 99%

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs

Zoni

Cremona

Fornaciari

2020

IEEE Embedded Syst. Lett.

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“…Dynamic Frequency Scaling (DFS) is cheaper than DVFS, since it does not scale the voltage at run-time. Moreover, the reduced scalability of voltage due to the technology evolution, makes the efficiency of DFS closer to the one of DVFS [17], [18]. In particular, Xilinx FPGAs that are more and more employed in both HPC and embedded projects, only offer DFS actuators.…”

Section: Background and Related Workmentioning

confidence: 99%

All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores

Zoni

Cremona

Fornaciari

2020

IEEE Trans. Comput.

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The Internet-of-Things (IoT) revolution fueled new challenges and opportunities to achieve computational efficiency goals. Embedded devices are required to execute multiple applications for which a suitable distribution of the computing power must be adapted at run-time. Such complex hardware platforms have to sustain the continuous acquisition and processing of data under severe energy budget constraints, since most of them are battery powered. The state-of-the-art offers several ad-hoc contributions to selectively optimize the performance considering aspects like energy, power, thermal or reliability. However, there is a need for a generic coordinated management strategy able to cope with all of these dimensions, while allowing the Operating System (OS) and the applications to "suggest" or constrain the actuation. This paper proposes a unified control-theoretic scheme to coordinate the design of energy-budget and energy allocation solutions for multi-cores. The proposed controller can work with any actuator and it can interact, at run-time, with both the applications and the OS to optimize the actuation signals steering the computing platform. Such control scheme offers the possibility to integrate any performance related policy in the form of an energy-allocation strategy, still ensuring the theoretic exponential stability of the overall controller if the actuation of the policy, coming from the OS and the applications, "is not too fast". To demonstrate the feasibility of our solution, we implemented the controller into a RISC multi-core running on the Xilinx Artix 100t FPGA device, available in the the Digilent Nexys4-DDR board. Results considering two actuators and both the quad-and the eight-core version of the considered computing platform, highlight the scalability of the proposed solution as well as an area overhead for the-all digital, on chip-controller limited to 0.86% (FFs) and 5.3% (LUTs) of the FPGA chip. We also considered a dynamic scenario validating the speed of the controller, where our framework has to face with modifications to the energy-allocation control policy carried out by the OS and the applications. The obtained results are collected by executing a huge mix of benchmarks and the statistical significance is accounted by executing each scenario 30 times. Such results are analyzed considering three quality metrics. First, the efficiency in exploiting the imposed budget (EF Fg) that is on average 98.27%. Second, the overflow of the actual average power consumption with respect to the assigned budget (OV Fg), which is limited to 1.43 mW on average. Last, the performance utility loss due to the control scheme that is limited to 1.87% on average.

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“…{VC count = VC count − 1 and packet be read from VCs} (9) end while (10) while (VC count be change) do (11) if (VC count = ) (12) {assign full flag to 1} (13) else if (VC count = 1) (14) {assign empty flag to 1} (15) else (16) {assign full flag and empty flag to 0} (17) end while Algorithm 4: VCs with SPS algorithm.…”

Section: Vlsi Designmentioning

confidence: 99%

“…Second, it uses clock-gating to reduce power consumption. Rosa et al [12] proposed dynamic frequency scaling in PE for NoC. It considers the communication and loading rate to control the router frequency to reduce the power consumption.…”

Section: Introductionmentioning

confidence: 99%

Design of Smart Power-Saving Architecture for Network on Chip

Lee

Huang

2014

VLSI Design

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In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in router are included. However, the router includes five I/O ports, and then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS), for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces 37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively.

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Power consumption reduction in MPSoCs through DFS

Cited by 21 publications

References 13 publications

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs

All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores

Design of Smart Power-Saving Architecture for Network on Chip

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