Power-delay-area efficient design of vedic multiplier using adaptable manchester carry chain adder

Katreepalli, Raghava; Haniotakis, T.

doi:10.1109/iccsp.2017.8286618

Cited by 9 publications

(1 citation statement)

References 7 publications

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“…In 2016, K. D. Rao et al has proposed VM based on the URDHVA TIRYAKBHYAM sutra and an N×N Vedic real multiplier with minimum path delay architecture is developed [31]. In 2017, R. Katreepalli and T. Haniotakis has (2017) proposed an efficient design of VM using Manchester Carry Chain (MCC) adder in a hierarchal approach [32]. In 2018, S. Sharma and Vangmayee has designed VM using Gate Diffusion Insulator (GDI) with reduced power and area [33].…”

Section: Vedic Multipliermentioning

confidence: 99%

A Systematic Journal of Multipliers Accuracy and Performance

2019

ijeat

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Low power and efficient architecture of computer arithmetic is demanded of real time Digital signal processing. Out of all arithmetic units, the multiplier is most important and frequently used arithmetic component in literature. As we know that there are many multipliers exist in the literature and everyone has his own proc-corns. But there is a gap in literature, no one gets compared all popular multiplier technique at same platform and discuss their advantages and limitations at one place. This research work outlines the most popular five multiplier techniques (like Wallace, modified, Vedic, Russian Peasant and Logarithm) and compares them, highlights merits, demerit for further improvements. This comprehensive study includes the systematic development, compares the latest design of every multiplier and justified that which one is better over other reported multiplier is also highlighted.

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Section: Vedic Multipliermentioning

confidence: 99%

A Systematic Journal of Multipliers Accuracy and Performance

2019

ijeat

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FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

Palanisamy

Ramachandran²

2020

Circuit Theory & Apps

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SummaryFor ultra‐low‐power applications, the computing components are smaller in size and consume less energy. In nonstationary signal analysis, the transformation plays an important role. Out of different transformation techniques, the most famous and dominant architecture is the discrete wavelet transform. The building block of the architecture should be optimized by all parameters. In this paper, the optimization was done on the power reduction and leakage current reduction. A new FinFET‐based lifting‐based wavelet architecture was proposed. Power gating and reversible logic methodology are proposed for the FinFET‐based transform to reduce the dynamic power by about 30%. The proposed FinFET‐based processing elements were utilized in the various blocks of the lifting‐based DWT architecture. The implementation was done in 32‐nm CMOS and FinFET technology. From the results, it has been investigated that the FinFET‐based circuits are efficient when compared with CMOS technology. This is due to the second‐order effects happening in CMOS circuits below 45 nm. The proposed design consumes less area and low leakage current and power when compared with the CMOS technology. Future trends of using multigate devices below 14 nm technology are presented finally.

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Power-Delay-Area Efficient Design and Implementation of Vedic Multiplier Using 14 nm Finfet Technology

Shetkar¹,

Waje²

2022

Lecture Notes in Electrical Engineering

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Power-delay-area efficient design of vedic multiplier using adaptable manchester carry chain adder

Cited by 9 publications

References 7 publications

A Systematic Journal of Multipliers Accuracy and Performance

A Systematic Journal of Multipliers Accuracy and Performance

FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

Power-Delay-Area Efficient Design and Implementation of Vedic Multiplier Using 14 nm Finfet Technology

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