Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Abstract

Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-inmemory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal−ferroelectric−metal− insulator−semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal−oxide−semiconductor FET, leading to a large MW (∼11 V), fast operation speed (<20 ns), and high endurance (∼10 11 cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.

Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems

“…Also, a row- and column-wise parallel programming method, which could decrease the training time, was experimentally proposed. At present, the demonstration of ferroelectric transistors for neuromorphic applications is usually done with small-density arrays or simulation methods without experimental validation of highly scaled, high-density neural networks based on ferroelectric transistors. − Further study needs to be done on the demonstration of a highly scaled transistor array for neuromorphic applications with considerations of array operations and their characteristics.…”

Novel strategies for low-voltage NAND flash memory with negative capacitance effect

“…The demand for increasing bit density in a storage device has been met by adopting the NAND flash architecture. [1][2][3][4][5] Then, their traditional planar device structure has innovatively evolved to vertically-stacked three-dimensional (3D) NAND flash technologies. [6][7][8][9] As the generation increases, an extreme mold height is required to integrate the maximum number of cells within a single string.…”

Unlocking the Potential of Hafnia Ferroelectrics: Achieving High Reliability via Plasma Frequency Modulation in Very High-Frequency Plasma-Enhanced Atomic Layer Deposition

“…The phenomenon of ferroelectricity has been thoroughly studied due to its potential uses in nonvolatile semiconductor devices, such as memory devices − energy harvesting, negative capacitance field effect transistors, , and sensors. , In recent times, there has been an increased level of attention toward Hf 0.5 Zr 0.5 O 2 (HZO) because it has the capability to demonstrate ferroelectric characteristics even when its thickness is less than 5 nm . In addition, the advancement of scaled 3D devices using HZO is anticipated to address the existing constraints in artificial intelligence performance due to memory capacity, as demonstrated by HZO ferroelectric memory devices. − Nevertheless, the primary limitation in deploying HZO memory devices is the wake-up effect, fatigue, and endurance caused by inevitable defects. , The wake-up and fatigue refer to the initial rise and subsequent decline in polarization of the ferroelectric device .…”