Power-delay optimizations in gate sizing

Sapatnekar, Sachin S.; Chuang, Weitong

doi:10.1145/329458.329473

Cited by 23 publications

(15 citation statements)

References 15 publications

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“…Since then many digital circuit design problems have been formulated as GPs or related problems. Work on gate and device sizing (the main topics of this paper) can be found in, e.g., Chu and Wong (2001b), Passy (1998), Cong and He (1999), Kasamsetty et al (2000), Matson and Glasser (1986), Pattanaik et al (2003), Shyu et al (1988), Sancheti and Sapatnekar (1996), Sapatnekar and Chuang (2000), and Sapatnekar et al (1993). These are all based on gate delay models that are compatible with geometric programming; see Kasamsetty et al (2000), Sakurai (1988), Sutherland et al (1999), Rubenstein et al (1983), and Abou-Seido et al (2004) for more on such models.…”

Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

“…Gate delay and power constraints are more complex, but also GP compatible when the models described below are used. (Several more sophisticated and accurate models are also GP compatible; see, e.g., Kasamsetty et al 2000, Sapatnekar andChuang 2000. ) For the design of gates with not too many inputs, it is common to distinguish and model the gate behavior for every input transition.…”

Section: Gate Designmentioning

confidence: 99%

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Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Sizing Optimization Via Geometric Programmingmentioning

confidence: 99%

Section: Gate Designmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

View full text Add to dashboard Cite

show abstract

“…In [22,23,24] gatesizing are based on the Lagrangian Relaxation technique. Other gate-sizing optimization algorithms techniques are proposed in [25,26,27,28]. These aforementioned gate-sizing optimization algorithms have been studied and used to design of digital circuits tolerant to process variations in order to minimize the impact on the circuit yield.…”

Section: Introductionmentioning

confidence: 99%

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

Rodríguez

Garcia-Gervacio

Leal

2018

IEICE Electron. Express

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It is known that process parameter variation degrades the performance of nanometer integrated circuits. Process variations reduce the maximum clock frequency operation of the chips. Diverse strategies have been proposed in the literature to overcome this issue, especially optimization algorithms (gate-sizing algorithms). However, convergence related problems have limited their use. In this work, a homotopy approach for the design of nanometer digital circuits tolerant to process variations is proposed. Two optimization strategies are developed in this work, the first based on the homotopy continuation method (HCM) and the second based on a modification of HCM, called in this work reboot homotopy continuation method (RHCM). Three logic paths were implemented to validate the algorithms. The optimization results obtained with the proposed strategies are compared with a Lagrange-Multipliers-based framework. Results obtained from HCM method are equivalent to the obtained with Lagrange Multipliers. On the other side, results obtained from the RHCM method are more accurate than the obtained with HCM and Lagrange Multipliers. Furthermore, the area used to implement the logic paths is lower when RHCM is applied. Moreover, the number of Newton-Rhapson iterations required to find the solutions are lower when RHCM is used; consequently, time computing is also lower.

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“…Gate sizing or the similar problem of transistor sizing has been an active research topic in recent years. Many approaches have been proposed before [13] [2] [11] [17]. Previous approaches that have taken power considerations into account during transistor sizing include [1] [10] [16].…”

Section: Introductionmentioning

confidence: 99%

“…Another linear programming based approach is presented in [16]. Power optimization with convex programming is proposed by Menezes, Baldick, and Pillegi [13]. In their work, timing constraint are constructed for every path in the circuit which can potentially generate a very large (exponential) number of constraints.…”

Section: Introductionmentioning

confidence: 99%

Soft Error-Aware Power Optimization Using Gate Sizing

Dabiri

Nahapetian

Potkonjak

et al.

Lecture Notes in Computer Science

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Abstract. Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEU) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at the sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a non-linear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit, we prove that it is sufficient to consider a linear number of constraints. As an important preprocessing step we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100% to 200% while, on average, the power saving is simultaneously decreased by less than 7% to 12% respectively, compared to the optimal power saving with no error rate constraints.

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Power-delay optimizations in gate sizing

Cited by 23 publications

References 15 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations

Soft Error-Aware Power Optimization Using Gate Sizing

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