Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform

Lee, Heeseok; Choi, Young-Dae; Song, Eunseok; Choi, Kyung Hwan; Cho, Tae-Je; Kang, Sayoun

doi:10.1109/ectc.2007.373945

Cited by 50 publications

(12 citation statements)

References 8 publications

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“…Interposer approaches utilizing thin-film multilayer interconnects with embedded passive devices (EPDs) have drawn attention as small form-factor packaging solutions [5]- [9].…”

Section: Introductionmentioning

confidence: 99%

Parylene Interposer as Thin Flexible 3-D Packaging Enabler for Wireless Applications

Maeng

Kim

et al. 2011

IEEE Trans. Microwave Theory Techn.

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This paper presents a novel, all-Parylene, thin, flexible 3-D packaging technology with an application demonstration of wireless powering. Parylene is utilized as a base substrate of a packaging interposer, and multilayer thin films are conformally stacked on the Parylene substrate. High-density (450 pF/mm 2 ) metal-insulator-metal capacitors are implemented with an ultrathin ( 47 nm) deposition of Parylene-N. The energy storage capabilities as well as RF characteristics are characterized. To demonstrate interposer applicability, an RF energy-harvesting study is performed by implementing a rectifier circuit on the Parylene interposer utilizing embedded capacitors of wide-ranging values and an antenna. Finally, substrate folding tests are performed to verify the applicability of the Parylene interposer in a flexible form factor without undergoing degradation in energy-harvesting capability. The thin-film flexible capacitors are demonstrated to not short-circuit even under the stress of folding the interposer.

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“…Interposer approaches utilizing thin-film multilayer interconnects with embedded passive devices (EPDs) have drawn attention as small form-factor packaging solutions [5]- [9].…”

Section: Introductionmentioning

confidence: 99%

Parylene Interposer as Thin Flexible 3-D Packaging Enabler for Wireless Applications

Maeng

Kim

et al. 2011

IEEE Trans. Microwave Theory Techn.

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“…For example, the simultaneous-switching-noise (SSN), it is caused by that the sudden changes in the current drawn by these functional chips. Also, an analysis of the impedance profile will give a good evaluation on the quality of the PDN [7]. Beside of the SSN and impedance-profile concerns, recently, to the impact on the PDN, there is the study on the resistance (R) and capacitance (C) of the TSV.…”

Section: Analysis II -The Impedance Analysis For Power Ground Designmentioning

confidence: 99%

Electrical analyses of TSV-RDL-bump of interposers for high-speed 3D IC integration

Sung

Chiang

Lee

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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As the progress of the packaging technology for the electronic consuming devices, the customer demands more and more. From the trend of the development on electronic devices, it shows that these demands require for more functions or higher density of devices within a limited space. By the capabilities of the 3D-IC technology, it could support such a design with multi-purposes including a smaller size, the high-speed and multi-functions. There are many approaches and technologies to make the 3D-IC. Amount of them, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path of the circuit in a device. And hence, this device may support a faster operation. In this study, we analyze the different designs based on two TSV technologies, the Cu-filled and coaxial-type TSVs. By using the simulation approach, we evaluate the performances of these proposed designs. And, the results in our study should have the benefits for designing the interposer substrates which are used for developing the 3D-IC.

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“…As a result the pitch size for devices assembled on FR4 is limited. Alternatively, the 3D-SiP based on silicon interposer platform is a very active area of ongoing research [1]. Due to the availability of wafer level processing, silicon substrates can be processed with the same pitch size and accuracy as the highly integrated components that will be assembled.…”

Section: Introductionmentioning

confidence: 99%

Photonic System-in-Package technologies using thin glass substrates

Brusberg

Schröder

Topper

et al. 2009

2009 11th Electronics Packaging Technology Conference

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The novel packaging approach glassPack is introduced as a System-in-Package (SiP) technology. Wiring length can be reduced and integration density can be increased by stacking different assembled substrate layers and interconnecting them resulting in 3D-SiP. Glass is an excellent substrate material because of matched coefficient of thermal expansion (CTE) to silicon, high thermal load, dielectric constant and high optical transparency over a wide wavelength range. Commercially available thin glass foils can be used as substrate materials for electronic and optoelectronic modules. The goal of our ongoing development is to make glass based packaging competitive with polymer (e.g. chip-in-polymer) or silicon based packaging (e.g. silicon-through-via, stacked dies by wire bonding). Our work is focused on conductor trace and through-via realization as well as optical lightwave circuit integration using glass as a substrate. For through-glass-vias, holes were drilled in glass wafers by different laser technologies and evaluated. Also, optical integration of waveguides and mirrors in glass substrates were investigated. This paper presents basic design rules and a selection of technologies for glass based SiP as well as a process flow for glass interposer applications.

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Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform

Cited by 50 publications

References 8 publications

Parylene Interposer as Thin Flexible 3-D Packaging Enabler for Wireless Applications

Parylene Interposer as Thin Flexible 3-D Packaging Enabler for Wireless Applications

Electrical analyses of TSV-RDL-bump of interposers for high-speed 3D IC integration

Photonic System-in-Package technologies using thin glass substrates

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