Power dissipation in optical and metallic clock distribution networks in new VLSI technologies

Testing of Interposer-Based 2.5D Integrated Circuits

“…One potential solution is to apply a single input clock to the die and derive multiple test clocks inside each block [24]. However, since all test clocks have the same activity, all the clock domains will toggle simultaneously; thus, a large number of scan flip-flops are likely to toggle together, leading to increased peak power, which can be much higher in comparison to the functional mode.…”

“…This has in turn led to significantly increased switching activity. One potential solution is to apply a single input clock to the SoC and derive multiple test clocks inside each block[24].Power savings can be achieved by staggering the test clocks during shift. Stagger can be achieved by ensuring that the clocks for different blocks have different duty cycles or different phases, thereby reducing the number of simultaneous transitions.The shift-clock stagger is implemented at the block level, which allows one block's scan chain to toggle at a time when the scan chains for other blocks remain quiet.…”

Architectural exploration of optical and electrical interconnects in MPSoC

“…For the past 20 years, the development of compact optical devices used for very short integrated communication links, have been studied extensively [7][8] [12]. These previous analyses show comparisons at the physical level (mainly with analytic comparisons) without the global view of a complex system.…”

Optical interconnections in future VLSI systems

“…The number of O/E converters is a particularly crucial parameter in the overall system since optoelectronic interface circuits at these points are of course necessary and consume power. The methodology and the assumptions used to properly design the optical H-tree are presented in detail in [4,5]. Figure 3 shows a picture of the optical H-tree test structure fabricated by LETI.…”

“…Finally, with 8172 output nodes in the considered case, the power consumed by the optical system becomes higher than that consumed by the electrical one. This fact can be easily explained taking into consideration the optical power budget [4,5]. Along with doubling the number of H-tree output nodes, the optical power, which needs to be emitted by the VCSEL to meet the overall system quality increases at least by 3.2 dB (because of the Y-splitters), which in turn increases the electrical power consumed by VCSEL by more than 100%.…”